7 segment display
 

hello im new to the forum
i am having problems implementing a 7 segment display to a predesigned adder, i do not require homework help but any feedback or a solution would be a great help

my code is as follows


library ieee;

use ieee.std_logic_1164.all;

-- definition of a full adder

entity FULLADDER is

port (a, b, c: in std_logic;

sum, carry: out std_logic);

end FULLADDER;

architecture fulladder_behav of FULLADDER is

begin

sum <= (a xor b) xor c ;

carry <= (a and b) or (c and (a xor b));

end fulladder_behav;



-- 4-bit adder

library ieee;

use ieee.std_logic_1164.all;



entity FOURBITADD is

port (e, f: in std_logic_vector(3 downto 0);

Cin : in std_logic;

Cout: out std_logic;
bcd: out std_logic_vector (3 downto 0);
segment: out std_logic_vector (6 downto 0));

end FOURBITADD;



architecture fouradder_structure of FOURBITADD is

signal g: std_logic_vector (4 downto 0); -- the carry
signal sum : std_logic_vector ( 4 downto 0); -- sum



component FULLADDER

port(a, b, c: in std_logic;

sum, carry: out std_logic);


end component;


begin

FA0: FULLADDER

port map (e(0), f(0), Cin, sum(0), g(1));

FA1: FULLADDER

port map (e(1), f(1), G(1), sum(1), g(2));

FA2: FULLADDER

port map (e(2), f(2), G(2), sum(2), g(3));

FA3: FULLADDER

port map (e(3), f(3), G(3), sum(3), g(4));

-- V <= c(3) xor c(4);

Cout <= g(4);

bcd <= sum;
begin
process (bcd)
begin
case bcd is
when "0000" => segment < = "1111110";
when "0001" => segment < = "0110000";
when "0010" => segment < = "1101101";
when "0011" => segment < = "1111001";
when "0100" => segment < = "0110011";
when "0101" => segment < = "1011011";
when "0110" => segment < = "1011111";
when "0111" => segment < = "1110000";
when "1000" => segment < = "1111111";
when "1001" => segment < = "1110011";
when others => segment < = "0000001";
end case;
end process;

end fouradder_structure;



any help would be great

Stevie