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Ardni 11-07-2008 12:05 PM

Avoiding metastability on asynchronous inputs
I am currently working on maintaining an old design which has quite a few asynchronous inputs. In the code a component was defined and instantiated for each of the inputs. Below is the code:

process (clk, rst) is
begin -- process
if rst = '1' then -- asynchronous reset (active high)
sgnl1 <= '1';
output <= '1';
elsif rising_edge(clk) then
sgnl1 <= input; -- asynchronous input transferred to sgnl1
output <= sgnl1 or input;
end if;
end process;

Normally I register the asynchronous input twice as shown below:

if rising_edge(clk) then
pre_signal1 <= m_signal1;
signal1 <= pre_signal1;
pre_signal25 <= m_signal25;
signal25 <= pre_signal25;

end if;
end process;

Are there any advantages to doing it the first way. To me it seems as though it may be less secure as only 1 flip flop is used. But the OR statement compares the registered signal and the input one cycle apart (all signals are active low so either signal being a logic '1' will produce a logic '1'. What happens if I try to OR a metastable signal with a 1 or a 0?

Also is there anything else to worry about when reading in an asynchronous signal other than the small chance of metastability?

Thanks for any help.

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