vhdl vector subtraction
Hi i have this code that doesn't work:
V_NEW_1 <= V_STORE_1 - GRAD_NORM_1;
where all are: SIGNAL std_logic_vector (7 down to 0)
and this warning:
There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Someone can help me?
How about giving then an init value like
Signal V_NEW1: std_logic_vector (7 downto 0) := "00000000";
thanks for the reply.
By initializing the vectors the code works, but V_NEW_1 take the value of V_STORE_1 and not the value of the difference beetween V_STORE_1 and GRAD_NORM_1.
V_NEW_1 <= (V_STORE_1 - GRAD_NORM_1);
Well - I got a feeling - the REAL problem could be - GRAND_NORM_1 never given a value in your circuit.
Please check this :-)
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