Velocity Reviews - Re: PN CODE GENERATOR

: نوشتcharles_el...@my-deja.com
> In article <38C76304.3994@aime.insa-tlse.fr>,
> MELET Patrick <melet@aime.insa-tlse.fr> wrote:
> > Hello,
> >
> > I'm searching a VHDL code for implement a Pseudo-Noise Code Generator.
> >
> > Thanks...
> > --
> > ************************************************
> > * Patrick MELET - Doctorant - PhD Student
> > * LAAS - CNRS / ERT ICARE
> > * 1, place Georges Brassens BP 73
> > * 31703 Blagnac Cedex
> > * France
> > * T�l : +33 (0)5 62 74 75 85
> > * Fax : +33 (0)5 62 74 75 87
> > * e-mail : melet@iut-blagnac.fr ou melet@laas.fr
> > * melet@aime.insa-tlse.fr
> > ************************************************
> >
> I am sure there are a number of ways to do this. A relatively simple,
> synthesizable way is to use a linear-feedback shift register (LFSR)
> with exclusive or (XOR) feedback. If the stages to be XORed and fed
> back are chosen properly, the result will produce a maximal-length
> pseudorandom sequence. A maximal-length sequence for an N-bit shift
> register will have (2**N) - 1 unique states. With exclusive or
> feedback the all zero state is excluded--with exclusive nor feedback,
> the all ones state is excluded. I have a package that I used in the
> past for some testbenches that implements some functions to produce
> these sequences. I never completed the package, but the functions that
> I did implement are correct. If you were to make a synthesizable
> register, you would probably not implement it as a function, but the
> logic to produce the sequence would be very similar and can be deduced
> from that for the functions. This package includes a feedback table for
> registers up to 32 bits in length. The VHDL code for the package is
> shown below. If you have any questions about this, please post them
> here or you may e-mail me at: charles.elias@wpafb.af.mil
>
> Charles
>
> Note: Due to the length of the package and to reduce possibility of
> typos, I did a cut and past to this posting. Unfortunately, this
> sometimes causes some garbling due to the line lengths. Sorry about
> this, but I think you will be able to make sense of it.
>
> CME
> ------------------------------------------------------------------------
> -----------------------------
> -- This package implements linear-feedback shift registers configured
> to produce maximal length
> -- pseudorandom sequences. N is the number of stages (bits), Bits to
> XOR are the bits to be XORed
> -- and fed back to bit( 0 ). For example, if N = 4, OutVec( 3 ) xor
> Outvec( 2 ) is fed back to
> -- OutVec( 0 ). Note that the last stage is always fed back. The
> fumctions are used as follows. For
> -- the first call, invec can have any value except all zeros (this is
> the one illegal state of the
> -- LFSR it will lock up in this state). The following calls to invec
> should be the outvec produced by
> -- the previous call (all zeros will never -- be produced).
> -- Example:
> -- TestVec <= ( others => '1' );
> -- for i in 1 to 10000 loop
> -- TestVec <= prand16( TestVec );
> -- end loop;
> --
> -- This code will produce 10000 different pseudorandom TestVec values
> ------------------------------------------------------------------------
> -----------------------------
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> package pkgpseudo is
>
> subtype bitvec16 is std_logic_vector( 15 downto 0 );
> subtype bitvec15 is std_logic_vector( 14 downto 0 );
> subtype bitvec14 is std_logic_vector( 13 downto 0 );
> subtype bitvec13 is std_logic_vector( 12 downto 0 );
> subtype bitvec12 is std_logic_vector( 11 downto 0 );
> subtype bitvec11 is std_logic_vector( 10 downto 0 );
> subtype bitvec10 is std_logic_vector( 9 downto 0 );
> subtype bitvec9 is std_logic_vector( 8 downto 0 );
> subtype bitvec8 is std_logic_vector( 7 downto 0 );
> subtype bitvec7 is std_logic_vector( 6 downto 0 );
> subtype bitvec6 is std_logic_vector( 5 downto 0 );
> subtype bitvec5 is std_logic_vector( 4 downto 0 );
> subtype bitvec4 is std_logic_vector( 3 downto 0 );
> subtype bitvec3 is std_logic_vector( 2 downto 0 );
>
> function prand16( signal invec : bitvec16 ) return bitvec16;
> function prand15( signal invec : bitvec15 ) return bitvec15;
> function prand14( signal invec : bitvec14 ) return bitvec14;
> function prand13( signal invec : bitvec13 ) return bitvec13;
> function prand12( signal invec : bitvec12 ) return bitvec12;
> function prand11( signal invec : bitvec11 ) return bitvec11;
> function prand10( signal invec : bitvec10 ) return bitvec10;
> function prand9( signal invec : bitvec9 ) return bitvec9;
> function prand8( signal invec : bitvec8 ) return bitvec8;
> function prand7( signal invec : bitvec7 ) return bitvec7;
> function prand6( signal invec : bitvec6 ) return bitvec6;
> function prand5( signal invec : bitvec5 ) return bitvec5;
> function prand4( signal invec : bitvec4 ) return bitvec4;
> function prand3( signal invec : bitvec3 ) return bitvec3;
>
> end package pkgpseudo;
>
> library ieee;
> use ieee.std_logic_1164.all;
> ------------------------------------------------------------------------
> -----------------------------
> -- N | Bits to XOR | N | Bits to XOR |
> -------------------------------------------------
> -- 3 | 2, 1 | 18 | 17, 10 |
> -- 4 | 3, 2 | 19 | 18, 5, 1, 0 |
> -- 5 | 4, 2 | 20 | 19, 16 |
> -- 6 | 5, 4 | 21 | 20, 18 |
> -- 7 | 6, 5 | 22 | 21, 20 |
> -- 8 | 7, 5, 4, 3 | 23 | 22, 17 |
> -- 9 | 8, 4 | 24 | 23, 22, 21, 16 |
> -- 10 | 9, 6 | 25 | 24, 21 |
> -- 11 | 10, 8 | 26 | 25, 5, 1, 0 |
> -- 12 | 11, 5, 3 ,0 | 27 | 26, 4, 1, 0 |
> -- 13 | 12, 3, 2, 0 | 28 | 27, 24 |
> -- 14 | 13, 4, 2, 0 | 29 | 28, 26 |
> -- 15 | 14, 13 | 30 | 29, 5, 3, 0 |
> -- 16 | 15, 14, 12, 3 | 31 | 30, 27 |
> -- 17 | 16, 13 | 32 | 31, 21, 1, 0 |
> ------------------------------------------------------------------------
> -----------------------------
> package body pkgpseudo is
>
> function prand16( signal invec : bitvec16 ) return bitvec16 is
>
> variable outvec : bitvec16;
> variable bit0 : bit;
>
> begin
> if ( invec = "0000000000000000" ) then
> outvec := ( others => '1' );
> else
> outvec := invec;
> bit0 := outvec(15) xor outvec(14) xor outvec(12) xor outvec(3);
> outvec := outvec( 14 downto 0 ) & bit0;
> end if;
> return outvec;
> end prand16;
>
> function prand15( signal invec : bitvec15 ) return bitvec15 is
>
> variable outvec : bitvec15;
> variable bit0 : bit;
>
> begin
> if ( invec = "000000000000000" ) then
> outvec := ( others => '1' );
> else
> outvec := invec;
> bit0 := outvec(14) xor outvec(13);
> outvec := outvec( 13 downto 0 ) & bit0;
> end if;
> return outvec;
> end prand15;
>
> function prand14( signal invec : bitvec14 ) return bitvec14 is
>
> variable outvec : bitvec14;
> variable bit0 : bit;
>
> begin
> if ( invec = "00000000000000" ) then
> outvec := ( others => '1' );
> else
> outvec := invec;
> bit0 := outvec(13) xor outvec(4) xor outvec(2) xor outvec(0);
> outvec := outvec( 13 downto 0 ) & bit0;
> end if;
> return outvec;
> end prand14;
>
> function prand13( signal invec : bitvec13 ) return bitvec13 is
>
> variable outvec : bitvec13;
> variable bit0 : bit;
>
> begin
> if ( invec = "0000000000000" ) then
> outvec := ( others => '1' );
> else
> outvec := invec;
> bit0 := outvec(12) xor outvec(3) xor outvec(2) xor outvec(0);
> outvec := outvec( 13 downto 0 ) & bit0;
> end if;
> return outvec;
> end prand13;
>
>
>
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