I am doing a timing simulation using Modelsim PE 6.2d of a design on an Altera 10Ke device. A Tco (clock to output) constraint was put in place in the design for an 8 bit register to the 8 bit wide data bus. The 8 bit signal must pass through a bit of combinational logic before arriving at the output.
Anyway the Tco constraint was inserted with a value of 10ns, but in Quartus the classic timing analyzer informs me that it canīt be done and that the time is 11 ns for each of the bits.
Now when doing the timing simulation and looking at the signals, I see a delay of 14 ns. Does anyone know why there could be a descrepancy of 3 ns between what Quartus says and what modelsim produces? (I donīt think its clock skew as I am lookinga t the clok signal in the register of the signal)
Iīm assuming that both Quartus and Modelsim are using the worst case (slowest) model. I was expecting that both times would have been quite close. Please let me know if anyone has any ideas?
|All times are GMT. The time now is 03:48 AM.|
Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.