Connection to global signals
Is it possible to connect a top level input to a global signal defined
in a package for synthesis purposes. I could see it as useful for
truely global signal such as a clock, reset or PCI bus (for example),
istead of having to drag them through the heirarchy.
Only Quartus complains with the error:
Error (10808): VHDL error at test_build.vhd(39): unsupported reference
to global signal or variable pci_data
Error (10784): HDL error at test_build.vhd(6): see declaration for
pci_data is declared in :
package pci_package is
signal pci_data : std_logic_vector(31 downto 0);
signal pci_addr : std_logic_vector(15 downto 0);
signal wr_en : std_logic;
end package pci_package;
and at the top level:
pci_data <= pci_data_in;
Am I outside the LRM. Are global signals really only for simulation??
(Modelsim doesnt complain at all.)
Re: Connection to global signals
> Is it possible to connect a top level input to a global signal defined
> in a package for synthesis purposes. I could see it as useful for
> truly global signal such as a clock, reset or PCI bus (for example),
> instead of having to drag them through the hierarchy.
Would I have to test sub-entities without a clock input?
> Am I outside the LRM.
No, you are ahead of the synthesis vendors.
-- Mike Treseler
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