Signal Processing Using VHDL
 

Hey Guys, VHDL HELP

I am a beginner to VHDL. I know how to write basic codes in VHDL.
I want to implement a Speech Recognition system using FPGA. So i want
to learn how to design the code in VHDL.
For that i have to learn the very basic of Signal Processing or
Analyzing using small inputs.

Can anyone give me start to it? PLEASE

thanx in adv

Re: Signal Processing Using VHDL
 

Get all the basic elements you need in your speech recognition system
Get to understand how to make a FIR filter, Multiplier, Adder,
Pipeline...etc..


On Oct 20, 11:40*pm, tang <tarangpatel2elect...@gmail.com> wrote:
> Hey Guys, VHDL HELP
>
> I am a beginner to VHDL. I know how to write basic codes in VHDL.
> I want to implement a Speech Recognition system using FPGA. So i want
> to learn how to design the code in VHDL.
> For that i have to learn the very basic of Signal Processing or
> Analyzing using small inputs.
>
> Can anyone give me start to it? PLEASE
>
> thanx in adv

Re: Signal Processing Using VHDL
 

I can talk about the way that I do things. For those kind of designs I
use some mathematics tools like Matlab. I don't use built-in
functions, rather I write them in my own in a VHDL style this helps me
while debugging my VHDL code. Additionally try to divide your codes
into small parts like FIR block, memory block, control block... this
also helps you to debug the code easily.

Good luck,

--enes

Re: Signal Processing Using VHDL
 

On Oct 20, 11:20*pm, Enes Erdin <eneser...@gmail.com> wrote:
> I can talk about the way that I do things. For those kind of designs I
> use some mathematics tools like Matlab. I don't use built-in
> functions, rather I write them in my own in a VHDL style this helps me
> while debugging my VHDL code. Additionally try to divide your codes
> into small parts like FIR block, memory block, control block... this
> also helps you to debug the code easily.
>
> Good luck,
>
> --enes

I'll strongly agree with what has been said. Nothing has been more
helpful (other than this group!) than breaking things into small
bits. Write, test, re-write, etc until each piece is bullet-proof -
garbage in and perfection out. This style also helps you when you are
farther down the line and can grab from your own toolbox of modules.

The other thing I would add is now is the time to develop good
practices. Make sure you're using "proper" libraries. Take a look at
your coding style and try to be consistant. For example, state
machines, pick a one, two, or three process style and stick with it.
Down the line you might change your mind but at least all your code up
to that point will be consistant and easy to modify.

Shannon

Re: Signal Processing Using VHDL
 

On Oct 21, 7:37 am, Shannon <sgo...@sbcglobal.net> wrote:
> On Oct 20, 11:20 pm, Enes Erdin <eneser...@gmail.com> wrote:
>
> > I can talk about the way that I do things. For those kind of designs I
> > use some mathematics tools like Matlab. I don't use built-in
> > functions, rather I write them in my own in a VHDL style this helps me
> > while debugging my VHDL code. Additionally try to divide your codes
> > into small parts like FIR block, memory block, control block... this
> > also helps you to debug the code easily.
>
> > Good luck,
>
> > --enes
>
> I'll strongly agree with what has been said. Nothing has been more
> helpful (other than this group!) than breaking things into small
> bits. Write, test, re-write, etc until each piece is bullet-proof -
> garbage in and perfection out. This style also helps you when you are
> farther down the line and can grab from your own toolbox of modules.
>
> The other thing I would add is now is the time to develop good
> practices. Make sure you're using "proper" libraries. Take a look at
> your coding style and try to be consistant. For example, state
> machines, pick a one, two, or three process style and stick with it.
> Down the line you might change your mind but at least all your code up
> to that point will be consistant and easy to modify.
>
> Shannon

Thanx guys...
Can anyone direct me to some sample codes or tutorials or any good
books to start with....
I found a code on FIR filter...but i am still confused about what will
the complete pieces and how will i connect them...
My very first confusion is how can i let my FPGA read and store the
incoming voice data?...

Re: Signal Processing Using VHDL
 

> I found a code on FIR filter...but i am still confused about what will
> the complete pieces and how will i connect them...
> My very first confusion is how can i let my FPGA read and store the
> incoming voice data?...

Start by simulating the code you have found. Do you know how your
system will be? What will supply data to your system? How large are
the packets? I think you will need external RAMs for this purpose. How
new you are I don't know but, perhaps you can try to simulate some RAM
operation, write some data to them and read by the help of a state
machine.

--enes

Re: Signal Processing Using VHDL
 

On Oct 22, 10:10*am, Enes Erdin <eneser...@gmail.com> wrote:
> > I found a code on FIR filter...but i am still confused about what will
> > the complete pieces and how will i connect them...
> > My very first confusion is how can i let my FPGA read and store the
> > incoming voice data?...
>
> Start by simulating the code you have found. Do you know how your
> system will be? What will supply data to your system? How large are
> the packets? I think you will need external RAMs for this purpose. How
> new you are I don't know but, perhaps you can try to simulate some RAM
> operation, write some data to them and read by the help of a state
> machine.
>
> --enes

For out initial design we will use the
- DSP micro controller to process the incoming analog siganl. It will
filter and sample the signal to digital.
- Then the software stored in the uC will frame and window the
digitized the signal.
- This will then be passed on to the FPGA which will start comparing
the words using HMM.

That is how i have designed the system so far.
As enes said i can store the processed digitized signal to the RAM ans
then use FSM to read in FPGA. But for initial simulation how can i
simulate the RAM. And most important do i still need the FIR filter
for my design or i can proceed with the comparison directly?

thanx

Merhaba,



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Bogazici Universitesi Elektrik-Elektronik Muhendisligi son sinif ogrencisiyim ve bitirme projesi olarak "speech recognition using FPGA technology" isimli konuyu almis bulundum ama su anda hicbir asama kaydedemis durumdayim. Acaba bana yardimci olabilirmisiniz ?

emren selam
 

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