Velocity Reviews - Unexpected output in Post-translate Simulation

Hello everyone,
I am very new in VHDL programming. For my work I am using ISE 10.1 and ModelSim XE III 6.3c. I am facing some problems in programming a simple code. the code is as follows:
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
port(
clk: in std_logic;
in_i1: in std_logic_vector(7 downto 0);
out_i1: out std_logic_vector(7 downto 0)
);
end test;

architecture a of test is
signal signed_out_i1: signed(7 downto 0);

begin

process(clk)
begin
if (clk'event and clk = '1') then
signed_out_i1 <= -signed(in_i1);
end if;
end process;

out_i1 <= std_logic_vector(signed_out_i1);

end a;
----------------------------------------

Problem # 1:

I want "signed_out_i1" will be changed to negative of "in_i1" at each clock change to 1. the behavioral (functional) simulation works alright and shows the expected result. But the in the Post-translate simulation the output is not as expected. I used the following testbench code:

--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_tb is
end test_tb;

architecture test_tb_arch of test_tb is
component test
port(
clk: in std_logic;
in_i1: in std_logic_vector(7 downto 0);
out_i1: out std_logic_vector(7 downto 0)
);
end component;

signal clk: std_logic;
signal in_i1,out_i1: std_logic_vector(7 downto 0);

begin
aaaa: test port map(clk,in_i1,out_i1);

process
begin
clk<='0';
in_i1<="11111111";
wait for 50 ns;

clk<='1';
in_i1<="00000001";
wait for 50 ns;

clk<='0';
in_i1<="00000001";
wait for 50 ns;

clk<='1';
in_i1<="11111111";
wait for 50 ns;
end process;

end test_tb_arch;

configuration AOA of test_tb is
for test_tb_arch
end for;
end AOA;
-----------------------------------------------------------
the expected output should be either "00000001" or "11111111". But in the output it shows "11001001" and "00110111". Can anyone explain what is the problem?

Problem # 2:
Another problem is that when I run Post-map Simulation or Post-route simulation in ISE 10.1 the simulation output is not shown in Modelsim. It shows the following ERROR in ModelSim:

# ** Warning: Design size of 12274 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Error: (vsim-SDF-3250) netgen/map/test_map.sdf(0): Failed to find INSTANCE '/UUT'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test_tb.mdo PAUSED at line 8

How to solve the problem?

I will be very greatful if anyone can help me to solve the problems.

Thanks and best regards,

Pantho