Multi-source on Integers in Concurrent Assignment.
I am using Xilinx ISE 10.1 to synthesize some code that simulates correctly. This is my first nontrivial (to me) FPGA/digital design. I am getting the error:
Multi-source on Integers in Concurrent Assignment.By commenting out clk_counter := clk_counter + 1, the error goes away (although there are different errors that appear).
My full code can be found here.
A Word document explaining what I am trying to do is here. In short, I am trying to build a serial to parallel radio decoder.
What am I doing wrong in the following code?
-- clock/timing process
-- asynchronous reset
if (reset = '1') then
current_state <= reset_st;
elsif rising_edge(clk) then
-- wrapping counter that keeps track of FPGA clocks
clk_counter := clk_counter + 1; -- fail
debug_current_counter <= clk_counter;
-- used for time-outs of polling in the state machine
-- fsm sets bit_poll and three_half_bit_time
if (bit_poll = '1' and clk_counter = three_half_bit_time) then
current_state <= store_bit_st;
current_state <= next_state;
I believe that the missing reset in the sensitivity list could be one problem
BUT - even if your using Shared Variables must there only be ONE process which controls this variable
Thank you for your response. That was my problem; I was assigning clk_counter from two processes.
As for the reset not being in the sensitivity list, doesn't that just mean that I have a synchronous reset. Can it cause problems the way it is currently written?
I believe the Tools will reconize your Asyncrone Clear (or Reset if you like) even without the missing signal
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