Small problem in VHDL
I'm new here and I meet a problem in VHDL, Could anybody please help me out?
The module I need
entity transfer is
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
output : out STD_LOGIC);
architecture Behavioral of transfer is
here if input is "01",output should be a 2 clock cycle long pulse
if input is "10", output should be a 4 clock cycle long pulse
if input is "11", output should be a 6 clock cycle long pulse
if input is "00", ouput remain low.
need sychronized sythesisable circuit...
input ONLY LAST ONE clock cycle
First - I believe you learn more by doing your homework yourself - but nevermind :-)
The most traditional solution to this problem would be a statemachine with say 13 state (one idle and 2+4+6)
This solution however based on a counter and variables.
Jeppe, thank you so much. actrually it is from a part of my project assignment. I don't know why but I just suddenly stuck at here for a few hours! I had thought about using counter but just cannot make it done. Maybe next time I should post my wrong code and you can point out my weakness in solving this kind of problem. Again, thanks for your self-explaining code.
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