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 Quarillo 07-31-2008 01:36 PM

RNG in VHDL

Hi!
I need a random number generator in VHDL.
So I already tried to use the following method:

library ieee;
use ieee.math_real.all; -- for UNIFORM, TRUNC
use ieee.numeric_std.all; -- for TO_UNSIGNED
....

process
-- Seed values for random generator
variable seed1, seed2: positive;
-- Random real-number value in range 0 to 1.0
variable rand: real;
-- Random integer value in range 0..4095
variable int_rand: integer;
-- Random 12-bit stimulus
variable stim: std_logic_vector(11 downto 0);
begin
-- initialise seed1, seed2 if you want -
-- otherwise they're initialised to 1 by default
loop -- testbench stimulus loop?
UNIFORM(seed1, seed2, rand);
-- get a 12-bit random value...
-- 1. rescale to 0..(nearly)4096, find integer part
int_rand := INTEGER(TRUNC(rand*4096.0));
-- 2. convert to std_logic_vector
stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));

But in my Math_real library there is no TRUNC-Function.

If I try to simulate it without the Trunc Function, the Behavioural Simulation works fine.
But my Synthesis Tool (Synplify) shows the following ERROR:

CD339 :"C:\Libero\Synplify\Synplify_902A2\lib\vhd\mat h_r eal.vhd":649:6:649:16|Right argument must evaluate to a constant integer power of 2

The error is in the following line in the math_real library File in the UNIFORM Procedure :

k := Seed1/53668;

Can anybody help me?!?
Thx a lot!

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