Xilinx floating-point core example please
I am looking for a VHDL example where someone has instantiated a Xilinx floating-point operator that was created with Core Generator.
I can create the core and I can get the template for my operator from the Library. I setup my entity and place the generated code. When I go to simulate, my result from the operation is all 'U's. I can post code later today.
Here is my code:
entity float4 is
a1: IN std_logic_VECTOR(31 downto 0);
b1: IN std_logic_VECTOR(31 downto 0);
operation1: IN std_logic_VECTOR(5 downto 0);
clk1: IN std_logic;
result1: OUT std_logic_VECTOR(31 downto 0));
architecture structure of float4 is
a: IN std_logic_VECTOR(31 downto 0);
b: IN std_logic_VECTOR(31 downto 0);
operation: IN std_logic_VECTOR(5 downto 0);
clk: IN std_logic;
result: OUT std_logic_VECTOR(31 downto 0));
mfc : myFloatCore
port map (
a => a1,
b => b1,
operation => operation1,
clk => clk1,
result => result1);
Note that the .xco file for myFloatCore is also visible in the project tree.
Have you changed the "maximum latency' option during the core design?
please change it to the minimum value and try simulating
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