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-   -   Process sensitivity list (http://www.velocityreviews.com/forums/t621148-process-sensitivity-list.html)

ferrari 06-19-2008 11:59 AM

Process sensitivity list
 
hi VHDL guys.
I'm a bit confused regarding the process sensitivity list,

as I've read in this book "McGraw Hill - VHDL Programming by Example - 4th Ed"
they say that " This list enumerates exactly which signals cause the process
statement to be executed. In this example, the list consists of a, b, c, d,
s0,and s1. Only events on these signals cause the process statement to
be executed."


if that was right, then i guess this code:

Code:

entity test is
 port (        din:  in bit;
                sel:  in bit_vector (1 downto 0);
                dout: out bit_vector (3 downto 0));
end test;

architecture behave of test is
begin
        process (din)
        begin
        case sel is
                        when "00" => dout<=('0','0','0',din);
                        when "01" => dout<=('0','0',din,'0');
                        when "10" => dout<=('0',din,'0','0');
                        when "11" => dout<=(din,'0','0','0');
        end case;
        end process;
end behave;

would not have produced those simulation results:

http://img378.imageshack.us/img378/4707/testqa2.jpg

and that is because as i understand, since din is constantly high, there are no events on "din" signal, thus the process would not be executed, not even if the signal "sel" changes, since it is not on the sensitivity list. is that right?
the problem is, that this process is still executed, even though there are no events on "din". maybe you guys can help me undersand why is this happening. maybe i don't understand the concept of this sensitivity list?
please help...

jeppe 06-19-2008 12:29 PM

Your welcome
Jeppe

Code:

entity test is
 port (        din:  in bit;
                sel:  in bit_vector (1 downto 0);
                dout: out bit_vector (3 downto 0));
end test;

architecture behave of test is
begin
        process (din, sel) -- All inputs must appear in order to produce combinatorial LOGIC
        begin
        case sel is
                        when "00" => dout<=('0','0','0',din);
                        when "01" => dout<=('0','0',din,'0');
                        when "10" => dout<=('0',din,'0','0');
                        when "11" => dout<=(din,'0','0','0');
        end case;
        end process;
end behave;


ferrari 06-19-2008 12:33 PM

jeppe, i know that. and still the code without (sel) in the sensitivity list, executes the same thing. can you please explain to me why is that?

when i compile the original code, there are no errors, it compiles fine and when i run simulation, i see the same thing as if sel was on the sensitivity list.

jeppe 06-19-2008 08:17 PM

Ok - You must realize that theres a touch of "black magic" connected with a synthesize tool ;-)

This my conclusion after several years with VHDL and "tools".

Jeppe

ferrari 06-20-2008 07:05 AM

thanx, you see, i'm a student, and a question like that just appeared on my final VHDL exam, and i guess i gave the wrong answer because i thought it would act differently without the SEL signal in the sensitivity list.

flintstone 06-20-2008 07:53 AM

What simulator were you using to get these results? Maybe it's just a bug or the simulator adds signals that are read in the process to the sensitivity list automatically.

ferrari 06-20-2008 11:56 AM

it's a standard Altera Quartus II 8.0 Web Edition. and i think it really does automatically adds signals that are read inside the process into the sensitivity list. problem is there is nothing in the theory about this, and i guess they cannot require me to know the specific phenomenons of each simulator, can they? the couse i've taken was a "VHDL" course, not "Altera Quartus II 8.0 Web Edition" behaviour course... right?

flintstone 06-23-2008 01:28 PM

Yes but as jeppe already said there is always some "black magic" to these tools. We had a similar bug where an event on a signal that was in the sensitivity list did not trigger process execution in the Modelsim SE, which is, from my experience, the best VHDL simulator available. This was clearly a bug and we had to play around with the sensitivity list to get the correct behaviour.

So this will happen to you again. Nevertheless you should try to get the free Modelsim-Altera or Modelsim-Xilinx editions, the Quartus Simulator surely is not the best available.

ferrari 06-24-2008 07:18 PM

thanx, i'll try to run this through modelsim and will post the results here.


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