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-   -   What am I missing... again? (http://www.velocityreviews.com/forums/t620385-what-am-i-missing-again.html)

rickman 06-16-2008 04:39 AM

What am I missing... again?
 
I wrote this debounce code and it did not behave the way I expected...

(btw, 'i' was used in a loop and the 5 was used outside of the loop
for a quick test)

if (EdgeDet(SW_D(i), SW_DD(i))) then
DebCntr(i) <= to_unsigned(Deb_Max_Cnt, 19);
if (DebCntr(i) = 0) then
Deb(i) <= SW_DD(i);
end if;
elsif (DebCntr(i) /= 0) then
DebCntr(i) <= DebCntr(i) - 1;
end if;

SW_D is the value of SW run through one FF. SW_DD is the value run
through a second FF. EdgeDet is defined to return either a boolean or
an SLV and is defined for a boolean as...

function EdgeDet (Val, Val_D : STD_LOGIC) return Boolean is
begin
return (Val = '1' xor Val_D = '0');
end EdgeDet;


The above code seems to set the counter to the max value by default
and let it count down by one when an edge is detected on SW. It is
supposed to do the opposite.

T try to debug the issue, I pulled the edge detect function outside
and assigned it to a signal...

SwEdge(5) <= std_logic(EdgeDet(SW_D(5), SW_DD(5)));

if (SwEdge(i) = '1') then
DebCntr(i) <= to_unsigned(Deb_Max_Cnt, 19);
if (DebCntr(i) = 0) then
Deb(i) <= SW_DD(i);
end if;
elsif (DebCntr(i) /= 0) then
DebCntr(i) <= DebCntr(i) - 1;
end if;

This worked correctly!!! Obviously there is something I am missing
here. I am 99.9% sure I did not change the meaning of the code by
these changes. But obviously did.

Rick

Thomas Stanka 06-16-2008 05:16 AM

Re: What am I missing... again?
 
On 16 Jun., 06:39, rickman <gnu...@gmail.com> wrote:
> if (EdgeDet(SW_D(i), SW_DD(i))) then

[..]
> SwEdge(5) <= std_logic(EdgeDet(SW_D(5), SW_DD(5)));


> This worked correctly!!! Obviously there is something I am missing
> here. I am 99.9% sure I did not change the meaning of the code by
> these changes. But obviously did.


An obvious change of the code is that second sollution will execute
the content of the if..then..else path be at least one simulation
delta later. I suppose it is executed one clock cycle later.

bye Thomas


rickman 06-17-2008 12:24 AM

Re: What am I missing... again?
 
On Jun 16, 1:16 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
> On 16 Jun., 06:39, rickman <gnu...@gmail.com> wrote:
>
> > if (EdgeDet(SW_D(i), SW_DD(i))) then

> [..]
> > SwEdge(5) <= std_logic(EdgeDet(SW_D(5), SW_DD(5)));
> > This worked correctly!!! Obviously there is something I am missing
> > here. I am 99.9% sure I did not change the meaning of the code by
> > these changes. But obviously did.

>
> An obvious change of the code is that second sollution will execute
> the content of the if..then..else path be at least one simulation
> delta later. I suppose it is executed one clock cycle later.


Thanks,

I don't know what I was thinking. When I read your post I thought I
must have mis-copied the code from the editor, and now I can't
recreate the problem. So I must have had a weird typo in the code and
the editing fixed it without my realizing it.

I find that the simulator will ignore some errors and synthesis will
ignore some errors, and they are not the same errors! Once I had a
bit constant of "0002" when I meant "0010" and the synthesis engine
took it! I have no idea what it created from that. But when it
didn't work I tried it in the simulator and of course it flagged the
error right away.

I guess I shouldn't code so late at night...

Rick :^)




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