Array initialisation in vhdl
i wanted to know whether we can initialise a vhdl array type variable or signal as shown below...
type example is array ( 1 to 10, 1 to 10 ) of any type
signal test: example;
for i is 1 to 10 loop
for j is 1 to 10 loop
test(i,j) <= "same 'array type' element"
when i tried in ISE 8.2i i got an error as test(i) is invalid array index
since im a beginner in VHDL ...u guys plz throw some light on this concept :veryprou:
would i and j be variables of the type integer?
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