How to acces to post-synthesis internal signals?
I don't know if it's possible to solve it, but my problem is as follows:
In the functional simulation, my design works fine, but when I run the post-synthesis simulation, the design doesn't works as it should. I only have access to the external ports; to detect the error, I should see the internal signals of design, but as the synthesizer changes the name of all those signals, I can't see them.
I know that I could see those signals adding ports to the top entity but there too many to do that.
Maybe it would be possible using records?
The code is in VHDL and the simulations are done with ModelSim and the synthesizer is XST, I'm working with a Xilinx FPGA.
I believe your using the starter version of Modelsim
Try the buildin-ISE simulator from xilinx - your able to "open" your design in a tree structure (usually lower left corner)
Add the signal you want to watch by "drag and drop" - restart the simulator and run the simulation agian (for specific time)
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