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tahder 03-18-2008 09:21 AM

mask generator
 
Hello everyone,
I am new to vhdl and I want to implement a synthesizable mask generator.
I thought about implementing it with a 2D array (like a ROM) that is usually seen in vhdl books.
My problem is that I'm stuck with generating the contents inside the array since an index will output a '1' only if an n-bit element is equal to another n-bit element. I don't want to have a build up of equality comparators. Is it possible to have only one comparator for the whole system? or a single row of comparators that will work for all the rows in the memory? I tried doing this:

architecture bhv of maskGen is

subtype patternArray is std_logic_vector (n-1 downto 0);
type referenceArray is array (r-1 downto 0) of patternArray;
signal memory : referenceArray;

-- this is for the magnitude comparator
component magComp
port (A, B : in std_logic_vector (n-1 downto 0);
EQ : out std_logic);
end component;

-- The behavioral architecture for magComp is only:
-- EQ <= '1' when A=B else '0';

begin
process (rst, clk, maskEn)
begin

if clk = '1' and clk'event then
if maskEn = '1' then
for j in 0 to r-1 loop
for i in 0 to n-1 generate -- this is line 69
magComp port map (A=>maskIn_P(i), B=>maskIn_R(j), EQ => memory(i)(j));
end generate;
end loop;
end if;
end if;

end process;
end bhv;


However, this gave me an error:
Line 69. parse error, unexpected GENERATE, expecting LOOP.

Can anyone explain why the code generated such an error?

I really do not want to implement the code above since it might result to horrendous amount of logic.
What do I do now?

Thanks,
tahder

jeppe 03-18-2008 10:23 AM

Hi tahder

Not sure - but I guess the generate statement not allowed inside a process.

try this instead


PHP Code:

----------------------------------------------------------------------------------
library IEEE;
use 
IEEE.STD_LOGIC_1164.ALL;
use 
IEEE.STD_LOGIC_ARITH.ALL;
use 
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mskgen is
   generic
nnatural := 10;
             
rnatural := 10);
    
portclk,maskEnstd_logic);
end mskgen;

architecture bhv of mskGen is
   subtype patternArray is std_logic_vector 
(n-1 downto 0);
   
type referenceArray is array (r-1 downto 0of patternArray;
   
signal memory,maskIn_P,maskIn_R referenceArray;

begin
    process 
(clkmaskEn)
    
begin
        
if clk '1' and clk'event then
            if maskEn = '
1' then
                for j in 0 to r-1 loop
                    for i in 0 to n-1 loop
                       if maskIn_P(i)=maskIn_R(j) then
                           memory(i)(j) <= '
1';
                        else
                           memory(i)(j) <= '
0';
                        end if;
                    end loop;
                end loop;
            end if;
        end if;
    end process;
end bhv; 

And your code:

Code:

architecture bhv of maskGen is

subtype patternArray is std_logic_vector (n-1 downto 0);
type referenceArray is array (r-1 downto 0) of patternArray;
signal memory : referenceArray;

-- this is for the magnitude comparator
component magComp
port (A, B : in std_logic_vector (n-1 downto 0);
EQ : out std_logic);
end component;

-- The behavioral architecture for magComp is only:
-- EQ <= '1' when A=B else '0';

begin
process (rst, clk, maskEn)
begin

if clk = '1' and clk'event then
if maskEn = '1' then
for j in 0 to r-1 loop
for i in 0 to n-1 generate -- this is line 69
magComp port map (A=>maskIn_P(i), B=>maskIn_R(j), EQ => memory(i)(j));
end generate;
end loop;
end if;
end if;

end process;
end bhv;


However, this gave me an error:
Line 69. parse error, unexpected GENERATE, expecting LOOP.

Regards
Jeppe

tahder 03-19-2008 01:51 AM

Hi jeppe

Thank you so much for helping me.


I had added some lines of code so that I could access a row for the output.

for j in 0 to r-1 loop
for i in 0 to n-1 loop
if maskIn_P(i) = maskIn_R(j) then
memory(i)(j) <= '1'; --THIS IS LINE 68
else
memory(i)(j) <= '0';
end if;
end loop;

end loop;
elsif readEn = '1' then
maskOut <= memory(conv_integer(address));
else
maskOut <= "ZZZZZ";
end if;
end if;

end process;


Here's my port declaration:

address : in STD_LOGIC_VECTOR (r-1 downto 0);
patternIn : in STD_LOGIC_VECTOR (n-1 downto 0);
referenceIn : in STD_LOGIC_VECTOR (r-1 downto 0);
maskOut : out STD_LOGIC_VECTOR (n-1 downto 0));



I got no error in checking the syntax but got one when I tried to view the RTL schematic.
line 68: Index value <8> is not in Range of array <memory<0>>.

I'm not sure but I have a feeling that the error is caused by this line
maskOut <= memory(conv_integer(address));

Is it necessary for n and r to be equal? I had tried letting n be equal to 8 and r to 32
but it won't synthesize. When I tried using your values which is 10 for both, it did
synthesize. So long as n and r are equal it synthesized. But I can't have have equal values for n and r
since my reference vector must be much longer than my pattern vector.

Thanks again,
tahder

jeppe 03-19-2008 08:13 AM

My "fast" answer without getting into details.
1) Have you tried this algoritme in other languages like C or Java.
2) Have you draw the data structures at a paper checking the flow.
3) A got a feeling your about to create a huge combinatorial network which in the end will take up to much space.
May be should you consider a "pipelined" design in which you works at parts of the arrays. This will however cost you time instead of logic.

Jeppe

tahder 03-21-2008 12:24 PM

jeppe,

1. I hadn't tried it yet in other languages.
2. I have been using paper and pen too for this thinking I might find some other way to manipulate the flow.
3. I am just considering 3 for n and 5 for r.

If I am able to find a way out of this I will post again (and will hope for your comments). Again, thank you. You and your site really enlightens!

rani 03-27-2012 05:18 PM

can you tell me how to do this in verilog..

jeppe 03-28-2012 10:08 AM

Nope :( verilog not among my "languages"

rani 03-28-2012 01:30 PM

no problem..can you plz tell me the logic..in gate level..then i can code it myself..because i dont know vhdl..if you could draw and show it would be very nice..thanks


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