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csosza3@gmail.com 04-11-2006 10:29 PM

inout problem
 
Hi,

I made a simple ram model to test inout but the testbench result not as
I expected.

If I remove the two last line
data <= "0011";
rw <= '0';
it is ok but if I add them the result is wrong. How can be modified
this design and the testbench to read and write data in normal way? I'd
like a simple ram model with working testbench.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram is port (
data : INOUT std_logic_vector( 3 downto 0 );
rw : IN std_logic );
end ram;

architecture arch of ram is
begin
process (rw)
variable data_s: std_logic_vector( 3 downto 0 ) := "0000";
begin
if ( rw = '0') then
data_s := data;
elsif ( rw = '1') then
data <= data_s;
end if;
end process;
end arch;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

entity ram_tb is
end ram_tb;

architecture TB_ARCHITECTURE of ram_tb is
component ram
port(
data : inout std_logic_vector(3 downto 0);
rw : in std_logic );
end component;

signal rw : std_logic;
signal data : std_logic_vector(3 downto 0);

begin

UUT : ram
port map (
data => data,
rw => rw
);

stm: process
begin
wait for 300 ns;

rw <= '1';
wait for 1300 ns;

data <= "0011";
rw <= '0';

wait;

end process;
end TB_ARCHITECTURE;


Thanks
Attila


Andy Peters 04-11-2006 11:01 PM

Re: inout problem
 
csosza3@gmail.com wrote:
> I made a simple ram model to test inout but the testbench result not as
> I expected.
>
> If I remove the two last line
> data <= "0011";
> rw <= '0';
> it is ok but if I add them the result is wrong. How can be modified
> this design and the testbench to read and write data in normal way? I'd
> like a simple ram model with working testbench.
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;


Why the std_logic_unsigned?????

> entity ram is port (
> data : INOUT std_logic_vector( 3 downto 0 );
> rw : IN std_logic );
> end ram;
>
> architecture arch of ram is
> begin
> process (rw)
> variable data_s: std_logic_vector( 3 downto 0 ) := "0000";
> begin
> if ( rw = '0') then
> data_s := data;
> elsif ( rw = '1') then
> data <= data_s;
> end if;
> end process;
> end arch;
>
> library ieee;
> use ieee.std_logic_unsigned.all;
> use ieee.std_logic_1164.all;
>
> entity ram_tb is
> end ram_tb;
>
> architecture TB_ARCHITECTURE of ram_tb is
> component ram
> port(
> data : inout std_logic_vector(3 downto 0);
> rw : in std_logic );
> end component;
>
> signal rw : std_logic;
> signal data : std_logic_vector(3 downto 0);
>
> begin
> UUT : ram
> port map (
> data => data,
> rw => rw
> );
> stm: process
> begin
> wait for 300 ns;
>
> rw <= '1';
> wait for 1300 ns;
>
> data <= "0011";
> rw <= '0';
>
> wait;
>
> end process;
> end TB_ARCHITECTURE;


Your problem is that you have two assignments to the same signal
(data). One assignment is in the RAM and the other's in the test
bench.

You need to tristate the RAM data, just like you'd do if you had a RAM
chip.

The testbench should tristate the data signal when it is doing a RAM
read.

Similarly, the RAM entity should tristate the data signal when you
write to the RAM.

-a



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