I have to code for the down counter. As u know , the down counter will take the data in put when the load is high( level trigger) and then when the load is low , they start to count down which is control by the "clock" . As i know is the "load" will be level trigger and the clock will be edge trigger.
The thing is , usually my frequency of the load usually less than the clock . For example , if i have the load frequency is 10khz , and suppose my data is 3 bits , then the clock frequency will be 2^3 * 10khz. It help me every (f= 10 khz), i need to take the data and count to 0 .
So the problem i facing is since the load is level trigger , then the counter start to count if the load is logic high----> some edge trigger clock , data wont count dow ---> that is not what i want.. I want it they load the data in and then the next cycle of the clock , they start to count down . ( to make sure that every value data load in , they will count down and reach zero)
Some suggestion is "load" signal , not using the 50% duty cycle, but then if i have 8 bits data , then the clock will be 2^8 times the load , then the load will be very small duty cycle.
So i create the new code , to procuce the signal S1 to act like the load signal. But there is some warning about " Timming analysis is analysing one or more combinational loop as a latch ( which is tmp signal in the below code)"
and " found 3 nodes in clock path at the ripple or gate clock..."
Here is the code : the S: load signal and C is the clock signal
process (S, C) is
if C'event and C = '0' then
S2 <= not S;
S1 <= S and S2;
process (S1, C, D)
if S1 = '1' then
tmp <= D;
elsif (C'event and C= '1') then
tmp <= tmp - 1;
end if ;
Q <= tmp;
I use the quartus II software. I am new in VHDL .
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