Velocity Reviews - Questa AVM

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- VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)

- - Questa AVM (http://www.velocityreviews.com/forums/t560734-questa-avm.html)

Hi is there anybody using questa...?

Ive attended a seminar on questa by mentor graphics 2 days back...

can you tell me what all are the benefits of using questa and how can
i enhance my simulation and save design time by using it..?

does it support synthesis...?
also whether any demo is available...?

thanks
knight

"knight" <krsheshu@gmail.com> wrote in message
news:5fae0ade-6a15-488c-b7dc-bce7950ce40e@b1g2000pra.googlegroups.com...
> Hi is there anybody using questa...?
>
> Ive attended a seminar on questa by mentor graphics 2 days back...
>
> can you tell me what all are the benefits of using questa and how can
> i enhance my simulation and save design time by using it..?
>
> does it support synthesis...?
> also whether any demo is available...?
>

One would think that if you had attended a seminar two days ago, that you
should be able to answer those questions....if it was a free seminar then it
appears you got your money's worth

KJ

"knight" <krsheshu@gmail.com> wrote in message
news:5fae0ade-6a15-488c-b7dc-bce7950ce40e@b1g2000pra.googlegroups.com...
> Hi is there anybody using questa...?
>
> Ive attended a seminar on questa by mentor graphics 2 days back...
>
> can you tell me what all are the benefits of using questa and how can
> i enhance my simulation and save design time by using it..?
>
> does it support synthesis...?

If you attended a seminar on Questa and asks if it supports Synthesis then
you were either asleep or Mentor gave a combined Questa/Catapult/Precision
presentation and decided to interleave the slides :-)

Questa is Modelsim-SE + Assertions + Functional Coverage + Testbench
automation + SystemC

Hans
www.ht-lab.com

> also whether any demo is available...?
>
> thanks
> knight

knight wrote:
> Hi is there anybody using questa...?

No. I have to struggle just to keep
the SE licenses in the budget.

> Ive attended a seminar on questa by mentor graphics 2 days back...

Oh no. I'll be getting more web-seminar email soon.

> can you tell me what all are the benefits of using questa and how can
> i enhance my simulation and save design time by using it..?

Are you sure you sure you weren't a presenter at the seminar? ;)
Unless you have already mastered vcom and vsim
the extra sizzle they are pitching now won't mean a thing.

> does it support synthesis...?

No, but since I worked out my design templates,
I spend very little time on synthesis.
It just works for verified code.

-- Mike Treseler

I attended Modelsim Questa AVM seminar yesterday. It was part of
XILINX PSI 2007.

Hans guessed correctly. It was a combined Questa/Catapult/Precision
presentation.

What I could able to understand was -
- As Hans said, Questa is Modelsim-SE + Assertions + Functional
Coverage + Testbench automation + SystemC + "SystemVerilog".
- Questa supports static verification which was not supported till
Modelsim 6.2(support dynamic verification).
- Questa come up with a new verification methodology.

And finally, the presentor asked seriously to look for some other
preofession if we are not thinking of updating ourselves with
SystemVerilog.

Regards,
JK

Hi,

On 14 Dez., 06:18, JK <krishna.januman...@gmail.com> wrote:
> Hans guessed correctly. It was a combined Questa/Catapult/Precision
> presentation.

Shame on the presenter, if you couldn't even answer basic questions
yourself after the presentation.

> What I could able to understand was -
> - As Hans said, Questa is Modelsim-SE + Assertions + Functional
> Coverage + Testbench automation + SystemC + "SystemVerilog".
> - Questa supports static verification which was not supported till
> Modelsim 6.2(support dynamic verification).
> - Questa come up with a new verification methodology.

Questa seems to me as a big nice tool for someone who could affort the
cost overhead, but it wont change market as long as it is siginificant
more expensive than a SE license.
The functionality is nice-to-have but not crucial for all designs I
expect to work on in the next month or years.

A good question for testbench automatisation is the question of the
time and effort needed to write a set of good and sufficient
assertions in order to enable the testbench automatisation.
I expect, that you could develop a lot of testbenches yourself in
that time.

> And finally, the presentor asked seriously to look for some other
> preofession if we are not thinking of updating ourselves with
> SystemVerilog.

This might be correct for pure Verilog-Companies. In VHDL-World, you
could expect benefit from SV only when using it as verification
language.
As long as SV for verification needs Questa licenses, only large
companies will or could afford to change from VHDL to SV. A major
commercial factor beside the license fee is the effort to change
existing inhouse resources (tools, rtl-code, verification code,
verification methodology) to SV.

I know only one company [1] in the German spoken area that switched
for all designs from VHDL to SV and this only for testing, the RTL
wont change to SV. I expect to see only few companies in europe
changing from VHDL to SV until 2010.

bye Thomas

[1] in fact only part of a big group

On Dec 14, 11:20 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
>
> Shame on the presenter, if you couldn't even answer basic questions
> yourself after the presentation.

Thomas,

Just a correction. Its not me, who couldn't answer basic questions
after presentor.
This thread is of knight... :)

As I also attended this seminar yesterday, I wanted to share how the
presentation went on...

Regards,
JK

"JK" <krishna.janumanchi@gmail.com> wrote in message
news:ca9aee7c-9209-42f8-8a4e-e14f73939576@s12g2000prg.googlegroups.com...
>I attended Modelsim Questa AVM seminar yesterday. It was part of
> XILINX PSI 2007.
>
> Hans guessed correctly. It was a combined Questa/Catapult/Precision
> presentation.
>
> What I could able to understand was -
> - As Hans said, Questa is Modelsim-SE + Assertions + Functional
> Coverage + Testbench automation + SystemC + "SystemVerilog".
> - Questa supports static verification which was not supported till
> Modelsim 6.2(support dynamic verification).
> - Questa come up with a new verification methodology.
>
> And finally, the presentor asked seriously to look for some other
> preofession if we are not thinking of updating ourselves with
> SystemVerilog.

"JK" <krishna.janumanchi@gmail.com> wrote in message
news:ca9aee7c-9209-42f8-8a4e-e14f73939576@s12g2000prg.googlegroups.com...
>I attended Modelsim Questa AVM seminar yesterday. It was part of
> XILINX PSI 2007.
>
> Hans guessed correctly. It was a combined Questa/Catapult/Precision
> presentation.

In that case I suspect knight dosed off when they changed presenters :-)

>
> What I could able to understand was -
> - As Hans said, Questa is Modelsim-SE + Assertions + Functional
> Coverage + Testbench automation + SystemC + "SystemVerilog".
> - Questa supports static verification which was not supported till
> Modelsim 6.2(support dynamic verification).
> - Questa come up with a new verification methodology.
>
> And finally, the presentor asked seriously to look for some other
> preofession if we are not thinking of updating ourselves with
> SystemVerilog.

<rant on>
This I find very annoying and narrow minded. I might be just me but I get
the impression that "some" EDA companies are on a crusade to convince us
that changing to SystemVerilog will solve all our design and verification
problem. I suspect the main reason is simply engineering overheads and
perhaps a hint of arrogance.

For those of you who are SystemVerilog evangelists (or VHDL evangelists for
that matter), let me tell you that the language itself is only a minor part
of the design process. Experience in design/verification, good coding
style, knowledge of other languages and disciplines, knowledge of the target
hardware etc etc is far more important than the language itself.

There is a lot of life and capability left in VHDL and I suspect that the
majority of the VHDL users (me included) only using a fraction of the
language. Yes I agree that SystemVerilog has some nice OO, assertions, fixed
point, a powerful constraint solver etc but most of these technologies are
available today for VHDL (and Verilog) users without resorting to
SystemVerilog.

I am pretty sure that in many years to come complex designs will be created
and verified in VHDL and Verilog and SystemVerilog and SystemC and C/C++ and
Handel-C and schematics ....
<rant off>

Hans
www.ht-lab.com

>
> Regards,
> JK

> In that case I suspect knight dosed off when they changed presenters :-)

Sure,
but this discussion is turning to be so valid and
interesting...... :-)

knight

JK wrote:

> And finally, the presentor asked seriously to look for some other
> preofession if we are not thinking of updating ourselves with
> SystemVerilog.

Ahh, glad to hear that fear was covered
as well as uncertainty and doubt ;)

The presenter better hope someone believes,
or he may be exploring career options.

-- Mike Treseler