Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   How to implement Random function (http://www.velocityreviews.com/forums/t55848-how-to-implement-random-function.html)

Karthikeyan Subramaniyam 02-24-2006 05:04 AM

How to implement Random function
 
Hi all,
I'm trying to port Verilog code to VHDL. In that I've $random system
task in verilog code. Can anyone support me to implement in VHDL
simplest way.

----
reg seq;
always
begin
#10 seq = $random;
end
----

like,

signal seq : std_logic;
.....

Thanks & Regards,
Karthik

Mike Treseler 02-24-2006 06:21 AM

Re: How to implement Random function
 
Karthikeyan Subramaniyam wrote:
> Hi all,
> I'm trying to port Verilog code to VHDL. In that I've $random system
> task in verilog code. Can anyone support me to implement in VHDL
> simplest way.


See the function "randomize" in the process tb_clk
in the testbench here:

http://home.comcast.net/~mike_treseler/test_uart.vhd


-- Mike Treseler

Barry Brown 02-24-2006 04:14 PM

Re: How to implement Random function
 
Package IEEE.math.real defines a function uniform for random variables.


"Karthikeyan Subramaniyam" <karthiks@toNomOucShsPemAi.coMm> wrote in message
news:dtm45f$3u3$1@home.itg.ti.com...
> Hi all,
> I'm trying to port Verilog code to VHDL. In that I've $random system
> task in verilog code. Can anyone support me to implement in VHDL
> simplest way.
>
> ----
> reg seq;
> always
> begin
> #10 seq = $random;
> end
> ----
>
> like,
>
> signal seq : std_logic;
> ....
>
> Thanks & Regards,
> Karthik





All times are GMT. The time now is 01:10 PM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.