Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   clock-domain-crossing simulation in Altera (http://www.velocityreviews.com/forums/t552155-clock-domain-crossing-simulation-in-altera.html)

kpram 11-15-2007 11:43 AM

clock-domain-crossing simulation in Altera
 
Hi all

Does anyone knows of a way to tell Quartus that a particular FF is a clock-domain-crossing FF so that post-route netlist instantiates a FF for that, which does not propagate "X".

In Xilinx this is done by applying the ASYNC_REG attribute. But haven't found anything similar in Altera.

regards,

Kostas


All times are GMT. The time now is 12:56 AM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.