![]() |
multisim 8 and VHDL/Verilog (cross post version)
Didn't know there was a sci.electronics.cad group... Any body have any
experience on the subject matter? Using VHDL components are seemless, however, how do you make your own and install it? The components wizard, when specifying VHDL component, looks for VHDL exectuable (.vx) files(presume .vdl/.vhdl are not .vx files.) How do you generate vx files? How does one specify an architecture to use, etc? There is absolutely no documents that discuss the matter @ EWB or on the web. Any help appreciated Monty |
| All times are GMT. The time now is 07:27 PM. |
Powered by vBulletin®. Copyright ©2000 - 2013, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.