Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   using 2 diffrent clock rates in a design. (http://www.velocityreviews.com/forums/t54417-using-2-diffrent-clock-rates-in-a-design.html)

Abs 01-25-2006 08:12 AM

using 2 diffrent clock rates in a design.
 
Hi friends.
how r u all doing,
well i have a doubt here. i have to write a tcl script to produce an
input from a file at a clock rate "clk1" and then capture the output of
the DUT at a diffrent clock rate say "clk2". now i have to give input
to DUT at a while loop and then capture at a diffrent loop. i'am facing
problem here/
any clues or ideas how to proceed..
plzz reply soon..

thanks

bye



All times are GMT. The time now is 04:24 PM.

Powered by vBulletin®. Copyright ©2000 - 2013, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57