Velocity Reviews

Velocity Reviews (
-   VHDL (
-   -   VHDL Case Statement (

The Hath 04-27-2007 04:38 PM

VHDL Case Statement
Is it possible to have a case statement where it only changes state on the positive edge of the clock? For instance in the statement below, I only want A to be changed on the positive (rising) edge of num.

case (num) is
when '0' =>
when others =>
end case;

For the when lines can I use:
when '0 and event'
or something like that?

All times are GMT. The time now is 04:26 AM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.