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The Hath 04-27-2007 04:38 PM

VHDL Case Statement
 
Is it possible to have a case statement where it only changes state on the positive edge of the clock? For instance in the statement below, I only want A to be changed on the positive (rising) edge of num.

case (num) is
when '0' =>
A<='0';
when others =>
A<=1;
end case;

For the when lines can I use:
when '0 and event'
or something like that?


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