please can explain the transport delay in vhdl?
what difference between inertial delay and transport delays?
Re: regards delays
On Mar 8, 5:14 am, "vijayakumar" <regupathivijayaku...@gmail.com>
> please can explain the transport delay in vhdl?
> what difference between inertial delay and transport delays?
Try simulating the following code and look at the differences between
signals 'b' and 'c'.
a <= '0, '1' after 10 ns, '0' after 11 ns;
b <= a after 20 ns;
c <= transport a after 20 ns;
Siganls 'b' and 'c' both model a 20 ns delay line where the output is
intended to follow the input signal 'a' (just 20 ns later). What
you'll see is that signal 'c' looks just like 'a' but shifted over by
20 ns but signal 'b' will show no activity until t=31 ns at which time
it will change from 'U' to '0', never having gone to a '1'.
The reason for this is the difference between 'inertial' and
'transport' delays. If you'll notice, signal 'a' is simply a 1 ns
wide pulse which happens to be less than the 20 ns of 'inertial'
delay. When multiple events happen on a signal within the inertial
delay interval, all but the last event is basically discarded. If you
changed a to generate 50 ns wide pulse (or anything greater than 20
ns) then signals 'b' and 'c' will both behave in the same manner and
will model what you would think a 20 ns delay line should be doing.
Depending on what you're modelling, both forms can be useful. For
synthesis, delays are not supported.
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