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A Sorting Circuit in Digital Logic DesignHello;
I am trying to implement a Linear Array Sort that takes in 10 8-bit inputs serially and outputs the inputs in increasing order. I figured out that Bubble Sort is the easiest kind of sort that can be implemented in hardware. The first step to implement this Linear Array Sorter was to read in the inputs. I used a Modulo 10 counter to read in the inputs from the user. Now how can I continue from here? I thought that using a 1-bit comparator (1-bit slicing) can work. But I then realized that I need buffers and other counters for further implementaion. Please, any ideas? I would really appreciate your help. Thanks. |

Re: A Sorting Circuit in Digital Logic DesignJohnathan Coll wrote:
> I am trying to implement a Linear Array Sort that takes in 10 8-bit > inputs serially and outputs the inputs in increasing order. I figured > out that Bubble Sort is the easiest kind of sort that can be > implemented in hardware. > The first step to implement this Linear Array Sorter was to read in the > inputs. I used a Modulo 10 counter to read in the inputs from the user. > > Now how can I continue from here? I thought that using a 1-bit > comparator (1-bit slicing) can work. But I then realized that I need > buffers and other counters for further implementaion. > Please, any ideas? I would really appreciate your help. I would: 1. Use a single process synchronous design. 2. Declare variables for the vector array,loop counters, and io shifters. 4. Code the sort algorithm directly with one compare/swap per tick. 5. sim the sort first, then do the load and unload modes. 6. Check synthesis using an RTL viewer. -- Mike Treseler |

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