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-   -   i need a help to solve a problem in VHDL (http://www.velocityreviews.com/forums/t376540-i-need-a-help-to-solve-a-problem-in-vhdl.html)

 emy86evil 11-21-2006 07:06 PM

i need a help to solve a problem in VHDL

hi every one

I have a problem in VHDL I need someone to explain it to me

the problem said:

(a)The diagram below show an 8-bit shifter that shhifts input one place to the left. Write a VHDL module for the shifter

and the figure has a ( A(7 downto 0)==>inputs // B(7 downto 0)==>outputs)
and has Rin /Lout

(b) write a VHDL module that multiplies an 8-bit input (C) by (101)2 to give a 11-bit product(D).This can be accomplished by shifting C two place to the lift and adding the result to C. Use Two of the modules written in (a) as a components and an overloaded operator fo addithion.

I solve Part (a) with no errors,and in part (b) I need someone who help me to solve it.

the code for par (a) is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shifter is
port(Clk: in bit;
Ain : in bit_vector(7 downto 0);
Bout : out bit_vector(7 downto 0));
end shifter;

architecture archi of shifter is

signal tmp: bit_vector(7 downto 0);

begin
process (Clk)
begin
if (Clk'event and Clk='1') then
for i in 0 to 6 loop
tmp(i+1)<=tmp(i);
end loop;

tmp(0)<=tmp(7);
end if;
end process;
Bout<=tmp;
end archi;

also I want to do a project in VHDL can someone give me a good topics for that?:roll:

 emy86evil 11-21-2006 08:20 PM

plz dont ignore me plzzzzz

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