FFT in VHDL (or Verilog) Tutorial
Can someone point me to simple implementation of FFT in VHDL(or
Verilog) with testbench and good step-by-step description. I have
implementation from Xilinx (which I will eventually use for hardware
implementation), but I find it rather confusing (lack of vhdl
experience). Algorithm used, # of points, Radix#, bit precision do not
matter, as I'm looking for tutorial-like implementation.
The best example of what I'm looking for is (found using google)
Re: FFT in VHDL (or Verilog) Tutorial
Tell me from which university and departmant you are, and also your
name, then I can answer your question. Of course for free ;-)
Student (confused) schrieb:
> Can someone point me to simple implementation of FFT in VHDL(or
> Verilog) with testbench and good step-by-step description. I have
> implementation from Xilinx (which I will eventually use for hardware
> implementation), but I find it rather confusing (lack of vhdl
> experience). Algorithm used, # of points, Radix#, bit precision do not
> matter, as I'm looking for tutorial-like implementation.
> The best example of what I'm looking for is (found using google)
FFT in VHDL
my name is Yassir Boukhriss. You can use the core generator available in ISE foundation, and instantiate that in your top level code.
xilinx fft core
I'm new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
I'd appreciate if some one could help me with this, I'd be so grateful indeed.
another question, in case I couldn't use the fft core I created an algorithm for a radix-2 and tried to write it in vhdl, but I'm not sure if I am going in the right way, following is the uncomplete code I'd appreciate if some one can tell me if it worth to complete the code like this or not;
PACKAGE untitled_pkg IS
TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF INTEGER;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
entity Hussain is
port(x:in vector_of_std_logic_vector16(0 TO 7);
y:out vector_of_std_logic_vector16(0 TO 7));
architecture Behavioral of Hussain is
variable temp:vector_of_std_logic_vector16(0 TO 7);
loop1: for l in 1 to log loop
loop2: for R in 1 to s loop
loop3: for n in 0 to (b-1) loop
wRom: case k is
when 0 => w := 2;
when 1 => w := 3;
when 2 => w := 4;
when 3 => w := 5;
when others => null;
and thanks in advance;
Not sure if your testbench is correct.
Try to simulate the design with another testbench.
You can download and use the automatic testbench
generators from http : // www . questatechnologies . com .
Send mails to support @ questatechnologies . com .
Hope this helps.
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