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dlamoris 11-11-2006 06:33 AM

Can someone please help?
Hello, I'm having some trouble trying to figure out what's wrong with this code. I'm doing an assignment where we're using two "line buffers" for writing to and reading from pixel information. The line buffer modules are given and I think it uses a primitive ramb16_s9_s9. What we're doing is that we have a stream of "lines", each 8 pixels, that need to be deinterlaced. We have 2 clocks, clk_27 is twice as fast as clk_13 and they're in sync. We're supposed to read from one buffer at twice the speed that it's writing to the other buffer, and they're not reading and writing from/to the same buffer at the same time (the read will read the same buffer twice in the amount of time it takes to write the other buffer once). So for example, when I finished writing one buffer (1,2,3,4,5,6,7,8), I will switch to the other buffer and maybe write (9,10,11,12,13,14,15,16). At the same time that I switched writing buffers, I will read from the buffer that I've just finished writing to. So when it's writing (9,10,11,12,13,14,15,16) at clk_13, I'll read (1,2,3,4,5,6,7,8,1,2,3,4,5,6,7,8) at clk_27.

But when I simulate it, the times when it switch gives me weird outputs.

EDIT:sorry I can't seem to make the spacing work here...basically, I'm writing 1 2 3 4 5 6 7 8 to one buffer, switch to another to write 9 10 11 12 13 14 15 16 while I read from the first one. The read output goes like 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 0 16 9 10 11 12 13 14...

It looks like the read is reading one cycle too early...but I'm not sure why. Below is the code for "deinterlace" (write_add and read_add refers to addresses). Does anyone see anything suspicious? Also, how would you look at all the internal signals when simulating in Modelsim (sorry I've rarely used Modelsim before...most of the time I just double click "simulate" in xilinx)


entity deinterlace is
rst : IN std_logic;
clk_13: IN std_logic;
Ri : IN std_logic_vector (7 DOWNTO 0);
Gi : IN std_logic_vector (7 DOWNTO 0);
Bi : IN std_logic_vector (7 DOWNTO 0);
clk_27: IN std_logic;
Ro : OUT std_logic_vector (7 DOWNTO 0);
Go : OUT std_logic_vector (7 DOWNTO 0);
Bo : OUT std_logic_vector (7 DOWNTO 0)
end deinterlace;

architecture behavioral of deinterlace is
signal write_add, read_add: std_logic_vector (10 downto 0);
signal read_en1, write_en1, read_en2, write_en2: std_logic;
signal R1, R2, G1, G2, B1, B2: std_logic_vector(7 downto 0);

WriteAddress: process (clk_13, rst)
if rst='1' then
write_add <= (others => '0');
elsif clk_13='1' and clk_13'event then
if write_add = "00000000111" then
write_add <= "00000000000";
write_add <= write_add + 1;
end if;
end if;
end process WriteAddress;

ReadAddress: process (clk_27, rst)
if rst='1' then
read_add <= (others => '0');
elsif clk_27='1' and clk_27'event then
if read_add = "00000000111" then
read_add <= "00000000000";
read_add <= read_add + 1;
end if;
end if;
end process ReadAddress;

Enable: process (clk_13, rst)
if rst='1' then
write_en1 <= '1';
write_en2 <= '0';
read_en1 <= '0';
read_en2 <= '1';
elsif clk_13'event and clk_13 ='1' then
if write_add = "00000000111" then
write_en1 <= not write_en1;
write_en2 <= not write_en2;
read_en1 <= not read_en1;
read_en2 <= not read_en2;
end if;
end if;
end process Enable;

linebuf1: entity work.line_buffer
port map(clk_27, read_add, read_en1, R1, G1, B1, clk_13, write_add, write_en1, Ri, Gi, Bi);

linebuf2: entity work.line_buffer
port map(clk_27, read_add, read_en2, R2, G2, B2, clk_13, write_add, write_en2, Ri, Gi, Bi);

muxout: entity work.mux2_8
port map(R1, R2, read_en2, Ro);

muxout2: entity work.mux2_8
port map(G1, G2, read_en2, Go);

muxout3: entity work.mux2_8
port map(B1, B2, read_en2, Bo);

end behavioral;

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