could you please explain me about the "bonded IOBs"
i am working on FPGA ,xilinx ISE 8.1 .
the target board is virtex 2vpro and it has 156 IBOs
i am able to synthesis my design with few errors , when i implement design i am not able to map.it throws a error saying that "The design is too large for the given device and package."
when i look at the summary i found that i have exceeded(256) the available
(156) limit "Number of bonded IOBs: 262 out of 156 167% (OVERMAPPED)"
so to decrease the over usage of bonded IOBs wht is that i have to DO?
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