i am trying to simulate a post-synthesis vhdl file generated by Xilinx Webpak , does anybody know how to include and use this file in modelsim independently ???:)
|All times are GMT. The time now is 07:40 AM.|
Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.