sensitivity list confusion
Hi all....i am student learning the VHDL coding this semester.....recently i found that the process statement with its sensitivity list does not work the way it is said in the text book.....although i never insert a particular signal into the sensitivity list....the output is changes whenever the particular signal changes value...... for example
entity h is
d : out STD_LOGIC;
c : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC
architecture h_arch of h is
d<=a and b and c;
the d value changes each time the value of either b or c changes although i mantain the value of a...
Can anybody help me in this problem???
I know this is super old but was this ever solved?
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