I'm having in trying to learn VHDL coding for use with XiLinx ISE WebPack.
I'm obviously new to VHDL but I understand the basics of VHDL for single entities, components and architecture. But it seems from all the examples that I look at that all the inputs and output are treated as external port signals. I'm having trouble seeing how one integrates two or more entities and how one distinguishes external port (chip) signals vs internal signals that don't come to the external chip. I'm having specifically two problems.
I have created a simple example that has two components (entities). One is an ADDER and the other is a DECODER. Nevermind, that this might be able to be done with a single entity. And nevermind this is a sill example. I'm not looking for a way to do this in one component or entity. I want to see an example with this done as two entities (or 2 components). I have specified and the rules of operation (NOT a better way of doing it, in one component). This will show me an example of integrating two entities (or components) and how to specify which signals are external and which are internal.
The block diagram, showing the ADDER and DECODER functional blocks are shown here:
First question: Is the ADDER and DECODER referred to as components, while the overall design might be the entity? What exactly is the difference between an entity and a component? Both seem similar.
Operation (in this sequence):
Basic example operation: The controller will setup A and B and raise "Mode" signal for only 1 Clk rising edge and then remove "Mode" signal.
Then on the next 4 Clk signals, X will pump out something based on the decode. It is irrlevant what the decode is but for argument sake, say that the 4 outputs are
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