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-   -   No clock signals found in design... (http://www.velocityreviews.com/forums/t365785-no-clock-signals-found-in-design.html)

Jerrie85 08-21-2006 11:26 PM

No clock signals found in design...
 
Whenever i synthesize i top level block in xilinx, i get this msg, "No clock signals found in design", so i dont get information about the clock speed or clock delay; this is wierd since i have a central clk signal that drives a lot of Flip flops

how do i correct this in synthesis? how do i make xilinx realize i have a clk sig that needs to be treated appropriately? i have no IBUFs, or CLKBufs in design

Jerrie85 08-24-2006 04:42 AM

i'm sure someone's got this before...does anyone know? pleasee help

Jerrie85 08-24-2006 04:42 AM

i'm sure someone's got this before...does anyone know? pleasee help


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