Using Altera LPM megafunctions in Quartus II and VHDL in general
 

Hello all.

I've successfully used an LPM counter in my code but I can't help
feeling that I just got lucky. Something seems missing. I used the
"Megawizard thingy".

I cut and pasted the component declaration from one of the files it
created and I cut and pasted the component instantiation from one of
the files it created (editing it for my code of course). Then I added
the vhdl file it created to my project in the project window. That's
it.

I feel like I'm getting away with this but it's not rigorous.
Shouldn't I need a library use clause or something? I'd like to say
again that everything is working fine but it just seems like something
is being assumed and when I try to move this code elsewhere its going
to break.

Shannon

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

Shannon wrote:

> I've successfully used an LPM counter in my code but I can't help
> feeling that I just got lucky. Something seems missing. I used the
> "Megawizard thingy".

Portability and simplicity are missing.
On the upside, you were able to get something
working without first learning vhdl for synthesis.

> I cut and pasted the component declaration from one of the files it
> created and I cut and pasted the component instantiation from one of
> the files it created (editing it for my code of course). Then I added
> the vhdl file it created to my project in the project window. That's
> it.

The alternative is to
declare a variable (or signal)
for the counter and add this
single line to your clocked process:

a_v := a_v + 1;

Then you can use the counter value a_v
for whatever you like in the rest of the
process. No components or instances required.

> I feel like I'm getting away with this but it's not rigorous.
> Shouldn't I need a library use clause or something? I'd like to say
> again that everything is working fine but it just seems like something
> is being assumed and when I try to move this code elsewhere its going
> to break.

If you don't mind the code clutter, all will be fine
until you change devices to one of the many
not made by Altera. Your lpm components are
just syntax errors to brands X, Y and Z.
This is deal you make with the wizard.

Learn synthesis or be prepared to redo
your design.

Have a look at the "clk enabled counters" example here
http://home.comcast.net/~mike_treseler/
for one way to write portable counters.

-- Mike Treseler

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

Mike Treseler wrote:
> Your lpm components are
> just syntax errors to brands X, Y and Z.
> This is deal you make with the wizard.

Actually 'LPM' (Library of parameterizable modules) is fairly portable
and is (I think) an EIA standard it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either, you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Kevin

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

KJ wrote:

> Actually 'LPM' (Library of parameterizable modules) is fairly portable
> and is (I think) an EIA standard

The lpm models were written by Altera and
were held by the now-defunct edif.org in
the public domain. The models had complex
string generics and were designed to be
fronted by a wizard application to
collect and fill in the option strings.
The files were last updated by Altera in 1999
and are now held by eia.

Xilinx has tolerated the models for synthesis
but you can find very little information
about lpm on their website.
Xilinx infers matching netlists, but
they are not named lpm.
Altera supports
the existing models, but there has not been
a new one in a long time.

> it's the MegaWizard produced files
> that are not and are specific to company 'A'. Within LPM, besides the
> stupid things like 'and', 'or', etc. there are some useful ones like
> 'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
> But you don't need a wizard to use these parts either,

True for Altera. Tough otherwise since the source
code is no longer public.

> you simply
> instantiate the lpm component hooking up signals, defining the
> generics, etc just like you would any other entity.

Quartus will also infer these for you from code.


-- Mike Treseler

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

On Fri, 18 Aug 2006 11:41:32 -0700, Mike Treseler
<mike_treseler@comcast.net> wrote:

>KJ wrote:
>
>> Actually 'LPM' (Library of parameterizable modules) is fairly portable
>> and is (I think) an EIA standard
>
>The lpm models were written by Altera and
>were held by the now-defunct edif.org in
>the public domain. The models had complex
>string generics and were designed to be
>fronted by a wizard application to
>collect and fill in the option strings.
>The files were last updated by Altera in 1999
>and are now held by eia.
>
>Xilinx has tolerated the models for synthesis
>but you can find very little information
>about lpm on their website.
>Xilinx infers matching netlists, but
>they are not named lpm.
>Altera supports
>the existing models, but there has not been
>a new one in a long time.
>
>> it's the MegaWizard produced files
>> that are not and are specific to company 'A'. Within LPM, besides the
>> stupid things like 'and', 'or', etc. there are some useful ones like
>> 'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
>> But you don't need a wizard to use these parts either,
>
>True for Altera. Tough otherwise since the source
>code is no longer public.
>
>> you simply
>> instantiate the lpm component hooking up signals, defining the
>> generics, etc just like you would any other entity.
>
>Quartus will also infer these for you from code.
>
>
> -- Mike Treseler

It seems a bit much just for a simple counter to have to write piles
of code like Mike linked to in his first response. That is why the lpm
counter seemed so simple to me. The lpm counter made the code look
nice and clean and neat and readable. Also, I assumed the lpm code
had been properly tested and vetted so that it reduces the amount of
code testing/debuging I need to do.

Harsh comments from Mike aside, what would be the "correct" way of
creating a "clean" reusable counter that includes: clock, count
enable, synchronous load, data in, and data out?

As an aside to Mike I'd like to add this:

I'm old school on the net and so my skin is pretty thick. But you
might want to conscider toning down your snide comments a bit. Act
like the person you are responding to is right in the room with you.
Maybe even act like he is a customer. I'm sure you have lots of good
things to say to help out newbies but acting like a jerk gets in the
way. I don't want to start a flame war here. My email address is
visible. I would be happy to take this offline.

Shannon

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

Shannon wrote:
> As an aside to Mike I'd like to add this:
>
> I'm old school on the net and so my skin is pretty thick. But you
> might want to conscider toning down your snide comments a bit. Act
> like the person you are responding to is right in the room with you.
> Maybe even act like he is a customer. I'm sure you have lots of good
> things to say to help out newbies but acting like a jerk gets in the
> way. I don't want to start a flame war here. My email address is
> visible. I would be happy to take this offline.
>
> Shannon

Shannon,

Sorry to butt in here, I have nothing to contribute to this discussion
technically except that as a beginner myself I'm very afraid of the
wizard approach to developing solutions. It seems like if you use the
wizard you can point and click and without really having any clue
what you just did, or what is going on behind the scenes, you've got
something to work! But what have you done? And I've seen as soon
as something comes up that isn't that trivial, you have to then go to
a massive amount of effort to work *around* the wizard abstraction
to add your own VHDL code and get it integrated...my experience
comes from watching someone else fight the Xilinx tools.

Bottom line there is the wizard seems to be a crutch that maybe makes
a newby feel productive, but in the end you might be better off
without it. Just edit the raw VHDL directly and build up a library of
your own VHDL source you can draw upon. The wizards seem to
be done for marketing hype -- do professionals in the industry who
are here to stay really depend on them? I don't know, I'm not a
professional yet.

Anyway the real point of this post -- I didn't read anything in Mike's
posts in this thread that seemed harsh or snide -- was there some
posting I missed? None of my business except as a curious lurker.

-Dave

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

>>> it's the MegaWizard produced files
>>> that are not and are specific to company 'A'. Within LPM, besides the
>>> stupid things like 'and', 'or', etc. there are some useful ones like
>>> 'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
>>> But you don't need a wizard to use these parts either,
>>
>>True for Altera. Tough otherwise since the source
>>code is no longer public.
>>
Synplicity also supports LPM which, for those people who use that tool,
makes the vendor choice moot since Synplify is not tied to brand 'A' or 'X'.

>>> you simply
>>> instantiate the lpm component hooking up signals, defining the
>>> generics, etc just like you would any other entity.
>>
>>Quartus will also infer these for you from code.
>>

While I agree that lpm_counter (and a good chunk of lpm as well) would be
better off written more clearly simply in VHDL or Verilog than it would be
to instantate the lpm part I do not agree that things like lpm_divide and
lpm_fifo would fit into that same mold at least not at this moment in time.
Re-writing code to implement a fifo or a divider is wasted time unless done
for the learning experience in which case it may be time well spent.

> It seems a bit much just for a simple counter to have to write piles
> of code like Mike linked to in his first response. That is why the lpm
> counter seemed so simple to me. The lpm counter made the code look
> nice and clean and neat and readable.

And that is pretty much the deciding factor....what makes the code "look
nice and clean and neat and readable" which I think would translate into
"more readily supportable" which should be a goal (albeit hard to measure)
of anyone writing code.

Mike's point (with which I agree) is that for the case of a counter in a
real design it will be much more understandable to simply write 'x := x + 1'
then it would be to instantiate lpm_counter.

> Also, I assumed the lpm code
> had been properly tested and vetted so that it reduces the amount of
> code testing/debuging I need to do.
>
Yes it has. If the tool supports it (and several do support lpm) than
you're correct.

KJ

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

Shannon wrote:

> Harsh comments from Mike aside, what would be the "correct" way of
> creating a "clean" reusable counter that includes: clock, count
> enable, synchronous load, data in, and data out?

Counters are easily written - like some other posters already said, just
declare a signal, and, when appropriate say something like

-- At the top of your file say
library ieee;
use ieee.std_logic_1164.all;
use ieee.num_std.all;

-- somewhere in the architecture declaration area, say
signal data_out : unsigned(0 to 999);
-- assume data_in to be an unsigned(0 to 999) on the entity port list
-- assume clock, count_enable and sync_load to be std_logic
....
-- Now, somewhere in the actual architecture body say

instance_name: process(clock, count_enable, data_in)
begin
if rising_edge(clock) then
if sync_load = '1' then
data_out <= data_in;
elsif count_enable = '1' then
data_out <= data_out + 1;
end if;
end if;
end process;

See how easy this is?

Now, with division, things are a lot more difficult. Especially if I can't
think my way out of using a divider, I'll allways use a wizard-generated
divider - greater minds than mine have sweated over the efficient
algorithms that are used in those beasts. For a multiplier I simply use
the '*' operator - life can be so simple...

Best regards,


Ben

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

Shannon wrote:

> I cut and pasted the component declaration from one of the files it
> created and I cut and pasted the component instantiation from one of
> the files it created (editing it for my code of course). Then I added
> the vhdl file it created to my project in the project window. That's
> it.

I think everyone in this thread has gone out on a tangent and he
responses have nothing to do with the question Shannon actually asked!?!

The point is not whether or not using the LPM is portable or even the
best solution for a counter (clearly it's not) but whether or not
Shannon is using the LPM component correctly.

In short Shannon, yes, that's exactly what you need to do. The
megawizard "thingy" merely assists in parameterising the component with
a point-and-click interface. You could of course achieve exactly the
same in pure VHDL yourself - you'd end up with the component declaration
and the VHDL file you included from the megawizard output.

Naturally you also need to instantiate your component, hence the second
step you took. The third step, adding the VHDL file, just imports the
(thin) wrapper that the megawizard created with all your parameters for
that particular instance.

As for including libraries etc, you notice the wrapper VHDL file you
included uses the altera_mf_components library.

Regards

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Re: Using Altera LPM megafunctions in Quartus II and VHDL in general
 

"Mark McDougall" <markm@vl.com.au> wrote in message
news:44e90499$0$4137$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
>
> I think everyone in this thread has gone out on a tangent and he
> responses have nothing to do with the question Shannon actually asked!?!
>

Well, to be fair there were some implicit questions in the original post
regarding portability of the code that has been produced. But I see you've
continued the tradition of going off on a tangent by yourself not answering
the one single question that was in the original post (pasted below for
those that forgot)

> I feel like I'm getting away with this but it's not rigorous.
> Shouldn't I need a library use clause or something?

The answer: No the library use clause is not needed if you use direct
instantiation (i.e.something of the form U1 : entity work.MyComponent port
map(...);

KJ