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=?ISO-8859-1?Q?Sch=FCle_Daniel?= 07-14-2006 01:59 PM

vhdl -> xml parser
 
Hello,

I am writing in Python small VHDL package parser
I wonder whether there is a free VHDL -> XML parser

so I could extract the information using one of available XML parsers

it could be a binary or source code(language doesn't matter)

Regards, Daniel

Mike Treseler 07-14-2006 04:55 PM

Re: vhdl -> xml parser
 
Schüle Daniel wrote:

> I am writing in Python small VHDL package parser
> I wonder whether there is a free VHDL -> XML parser


A VHDL source file is not valid XML so
maybe you mean a text to XML converter.

I don't understand how this
would help with parsing a VHDL package.

-- Mike Treseler

Amal 07-14-2006 07:07 PM

Re: vhdl -> xml parser
 
Any language including HDLs can be parsed to a Abstract Syntax Tree or
a Control/Data Flow graph and this intermediate format can be saved in
say XML. And other tools (like simulators, synthesis, formal, ...) can
use this XML to do some kind of processing or manipulate the tree and
display it....

EdaXML or other standards are coming that use XML for this. You can
find some information on:
http://xml.coverpages.org/xmlAndEDA.html
More examples here:
http://www.moxon.com/2001/11/16/chan...111161130.html

I can imagine big EDA venors already use some sort of XML
representation. Synopsys's CoreTools (CoreAssembler, CoreCunsultant),
and Mentor's Platform express use SPIRIT
(http://www.spiritconsortium.com) for IP integration using XML.

I guess a starting point is to do the parser and then define the XML
representation and dump the parse tree or Control/Data Flow graph in
XML.
-- Amal


Ira Baxter 07-15-2006 07:27 PM

Re: vhdl -> xml parser
 
"Amal" <akhailtash@gmail.com> wrote in message
news:1152904077.779523.115060@m79g2000cwm.googlegr oups.com...
> Any language including HDLs can be parsed to a Abstract Syntax Tree or
> a Control/Data Flow graph and this intermediate format can be saved in
> say XML. And other tools (like simulators, synthesis, formal, ...) can
> use this XML to do some kind of processing or manipulate the tree and
> display it....
>
> EdaXML or other standards are coming that use XML for this. You can
> find some information on:
> http://xml.coverpages.org/xmlAndEDA.html
> More examples here:
> http://www.moxon.com/2001/11/16/chan...111161130.html
>
> I can imagine big EDA venors already use some sort of XML
> representation. Synopsys's CoreTools (CoreAssembler, CoreCunsultant),
> and Mentor's Platform express use SPIRIT
> (http://www.spiritconsortium.com) for IP integration using XML.
>
> I guess a starting point is to do the parser and then define the XML
> representation and dump the parse tree or Control/Data Flow graph in
> XML.
> -- Amal


Our DMS Software Reengineering Toolkit parses Verilog and VHDL
in several dialects and can export XML. We don't often recommend
this option because the XML is usually enormous. YMMV.

http://www.semanticdesigns.com/Produ...MSToolkit.html


--
Ira Baxter, CTO
www.semanticdesigns.com





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