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-   -   How do I do a conditional statement in a constant statement? (http://www.velocityreviews.com/forums/t26298-how-do-i-do-a-conditional-statement-in-a-constant-statement.html)

 tkvhdl@gmail.com 12-15-2005 11:48 PM

How do I do a conditional statement in a constant statement?

I'd like to do the equivalent of
constant X : integer = (A > B) ? A : B;
in VHDL, where A and B are either constants of generics
Obviously VHLD does not use the "?" operator, but I tried things such
as
constant X : integer = A when (A>B) else B;
and that doesn't work.
This is quite straightforward with Verilog Parameters so it is not
unreasonable to do this.
Is it possible in VHDL ?

 Mike Treseler 12-16-2005 12:31 AM

Re: How do I do a conditional statement in a constant statement?

tkvhdl@gmail.com wrote:
> I'd like to do the equivalent of
> constant X : integer = (A > B) ? A : B;
> Is it possible in VHDL ?

Yes, but I have to write the function myself:
function big_int (arg_a : integer;
arg_b : integer)
return integer is
begin
if arg_a > arg_b then
return arg_a;
else
return arg_b;
end if;
end function big_int;

constant X_c : integer := big_int(42,43);

-- Mike Treseler

 allanherriman@hotmail.com 12-16-2005 10:21 AM

Re: How do I do a conditional statement in a constant statement?

tkvhdl@gmail.com wrote:
> I'd like to do the equivalent of
> constant X : integer = (A > B) ? A : B;
> in VHDL, where A and B are either constants of generics
> Obviously VHLD does not use the "?" operator, but I tried things such
> as
> constant X : integer = A when (A>B) else B;
> and that doesn't work.
> This is quite straightforward with Verilog Parameters so it is not
> unreasonable to do this.
> Is it possible in VHDL ?

I believe this bug in the language will be fixed in VHDL-200x, proposal
FT10B. (I just read the document, and it's not quite clear whether
this will work for an initialiser in a declarative region. Hmmm.)

Until then, Mike's suggestion will work for you.

Regards,
Allan

 tkvhdl@gmail.com 12-16-2005 06:13 PM

Re: How do I do a conditional statement in a constant statement?

thanks.
Glad to see this will be fixed in new VHDL!

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