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Info on packing regular tree-like structures into rectangles?

Hi,
I got thinking about recursive design of circuits in VHDL I created a
recursive circuit and got it
to simulate correctly but then had the thought that the RTL is a binary
tree of similar interconnect with each leaf being the same.
When this gets synthesized and layed out I guess that the regularity is
lost unless layed out by hand.

If I were to lay this out by hand, are their any existing papers on
packing such regular structures into rectangular spaces?

Are there any layout and routing tools designed for such tasks?

 Ralf Hildebrandt 12-06-2005 03:56 PM

Re: Info on packing regular tree-like structures into rectangles?

f'up to comp.lang.vhdl

> I got thinking about recursive design of circuits in VHDL I created a
> recursive circuit

Hmm .. what do you mean with "recursive circuit"? Eighter the
transistors / cells / macroblocks are implemented or not.

You may design a component, that is used by a controller (like a FSM),
that realizes a recursive algorithm, but then not the circuit is
recursive - only the algorithm is.

> When this gets synthesized and layed out I guess that the regularity is
> lost unless layed out by hand.

Why do you care about regularity of the layout of a digital circuit?
Except for signal delays there is no reason to think about the layout -
AFAIK.

A HDL is such a wounderful thing, that seperates layout problems from
functional behavoir.

Ralf

Re: Info on packing regular tree-like structures into rectangles?

Hi Ralf,

You can instantiate a component inside itself, and instantiation can be
controlled with "if" conditional statements.
Use changing generic values, e.g. count down a generic parameter for
successive instantiations, and use the generic to control what is
instantiated at each recursive instantiation level and also ensure that
the recursive instantiation stops.

What you design by this method can be very large and very regular from
little code. Other large regular structures (memories are the most
obvious example), have customized layouts.
If your RTL instantiates a large rectangular array of similar
structures with similar interconnectivity you might want to be able to
tile similar blocks and inter-block signals in the layout.

I am producing a binary tree of similar tiles and was thinking about
laying it out efficiently.