> example.. once we have designed a vhdl code. verified the output in
> testbench. how do we proceed next. synthesis is the next step if 'am
> not wrong.
For a synchronous design,
synthesis is a detail
compared to writing, simulating
and debugging your vhdl code.
For a first pass, you pick a device and
a directory, list the source files, push
a button. When it's done, start the hdl viewer
and see how it did.
-- Mike Treseler
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