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CODE_IS_BAD 09-05-2005 06:10 AM

Reading internal signals through a testbench.
 
Hi all,
Through a testbench (Verilog or VHDL), how do I read the values of
signals of a sub module through a top module? This is required to match
and assert if the program is working correctly. Please help. Thank you.

Best Regards,


Mike Treseler 09-05-2005 06:37 AM

Re: Reading internal signals through a testbench.
 
CODE_IS_BAD wrote:

> Through a testbench (Verilog or VHDL), how do I read the values of
> signals of a sub module through a top module?


http://groups.google.com/groups?q=vhdl+port+spy+package

vizziee@gmail.com 09-06-2005 04:55 AM

Re: Reading internal signals through a testbench.
 

> Through a testbench (Verilog or VHDL), how do I read the values of
> signals of a sub module through a top module?

Use the 'signal spy' feature of ModelSim (but before that, check if
your version of ModelSim supports it or not).



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