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mike 07-19-2005 04:25 PM

timing simulation problem
 
Hi,

I want that u help me if u can:

I use the XST tool for synthesis and implementation and i choose to
make the RAM whowever when i make the timing simulation with the
modelsim SE ( with sdf file of ram) i never see the data in
output....for this i want that u can say me where is my error....

Thanks for helping me

These are the files:



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram is
generic(DEEP: integer := 4;
WIDTH:integer := 8);
port(wr,clk:std_logic;
adram:in std_logic_vector(DEEP downto 1);
data_in: std_logic_vector (WIDTH downto 1);
data_out:out std_logic_vector (WIDTH downto 1));

end ram;

architecture beh_ram of ram is

begin
process_ram: process(clk)
type memory is array (15 downto 0) of std_logic_vector (width
downto 1);
variable mem : memory;
begin
if clk ='1' and clk'event then
data_out <= ( others => '0');
if wr ='1' then
mem(CONV_INTEGER(adram)):=data_in;
else
data_out <=mem(CONV_INTEGER(adram));
end if;
end if;
end process;
end;



Its testbench

-- VHDL Test Bench Created from source file ram.vhd -- 15:25:15
07/10/2005
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;

ENTITY ram_tb IS
END ram_tb;

ARCHITECTURE beh OF ram_tb IS

COMPONENT ram
generic(DEEP: integer := 4;
WIDTH:integer := 8);
PORT(
wr : IN std_logic;
clk : IN std_logic;
adram : IN std_logic_vector(4 downto 1);
data_in : IN std_logic_vector(8 downto 1);
data_out : OUT std_logic_vector(8 downto 1)
);
END COMPONENT;

SIGNAL wr : std_logic;
SIGNAL clk : std_logic:='0';
SIGNAL adram : std_logic_vector(4 downto 1);
SIGNAL data_in : std_logic_vector(8 downto 1);
SIGNAL data_out : std_logic_vector(8 downto 1);

BEGIN



wr <='1' after 9 ns,'0' after 69 ns;

clk <= not clk after 10 ns;


adram <= "0000" after 9 ns,"0001" after 29 ns,"0010" after 49 ns,
"0000" after 69 ns,
"0001" after 89 ns,"0010" after 109 ns;

data_in <= "00000001" after 9 ns,"00000010" after 29 ns,"00000011"
after 49 ns;

test_design: ram generic map(deep => 4,
width => 8)
PORT MAP(
wr => wr,
clk => clk,
adram => adram,
data_in => data_in,
data_out => data_out
);

END;



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