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-   -   Integer to std_logic_vector? (http://www.velocityreviews.com/forums/t23794-integer-to-std_logic_vector.html)

 Sebastian Eggers 06-29-2005 11:21 PM

Integer to std_logic_vector?

Hi,

i have to count several values from 0 to 99, at the moment i do it in an
array of integer 0 to 99.

As output-port i use a std_logic_vector(6 downto 0), but i may change
this if necessary.

How can i convert the integer to the vector? i have no idea and not
found any solutions yet. Any hint would be helpful

thanks
Sebastian

 Neo 06-30-2005 04:40 AM

Re: Integer to std_logic_vector?

use the conversion functions in the ieee numeric package or the
std_logic package

 ALuPin@web.de 06-30-2005 08:13 AM

Re: Integer to std_logic_vector?

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

conv_std_logic_vector(7, 9);

converts integer 7 to a std_logic_vector with 9 bits.

Rgds
André

 Nicolas Matringe 06-30-2005 09:09 AM

Re: Integer to std_logic_vector?

> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
>
> conv_std_logic_vector(7, 9);
>
> converts integer 7 to a std_logic_vector with 9 bits.

Nope! Please stop using std_logic_arith package.

use ieee.numeric_std.all

std_logic_vector(to_unsigned(natural_number, nb_bits));

Nico

 Galloth 11-09-2006 10:58 PM

Why we should stop using std_logic_arith package?

 Vivek Dhiman 07-26-2010 06:35 AM

converts integer to a std_logic_vector

It's simple firstly you should include these libraries
------------------------------------------
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
-------------------------------------

now suppose you have declared
signal x : integer;
signal sig : std_logic_vector (7 downto 0); --- (I am taking here length as 8 you take as much as you want)

-------------------------------------------------
x <= 2;
sig <= std_logic_vector (to_unsgined(x,8 )) -- x is the integer and 8 is the length of std_logic vector sig . If your siganl's length is n (suppose) then you have to write...

sig <= std_logic_vector (to_unsgined(x,n)) -- replace n by length of the vector decalred by you.

 joeblow 07-26-2010 02:35 PM

-- Generally preferably to only use "official" IEEE libraries
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

-- ...

-- "natural" means >= 0. Add range to x to help synthesis
constant NUM_BITS : natural := 8;
signal x : natural range 0 to 2**NUM_BITS-1;
signal vect : std_logic_vector(NUM_BITS-1 downto 0);

-- ...

-- By using LENGTH attribute, any change to vect is handled automatically
-- Could also just use NUM_BITS
x <= 2;
vect <= std_logic_vector(to_unsigned(x, vect'LENGTH));

The above code might look a little more complex, but by using constants and attributes, your code will be much more forgiving of changes in the future.

 debayan_p 08-03-2010 03:52 PM

I guess using IEEE official libraries is better coz they will not cause synthesis problems at a latter stage.

There are many synthesis tools, all of them don't follow the same libraries!!

Cheers,
Debayan

 Fleetfoot 11-11-2011 10:52 AM

Is there a way to do this when the integer is a generic? The LENGTH attribute doesn't apply and I need something equivalent to declare vect (in the above example) as:

signal vect : std_logic_vector(x'HIGH-1 downto 0);

This is legacy code that is being upgraded and the module is used in various places with different generic values from 13 to 25000 so using a single common width is not feasible.

Thanks
George

 joris 11-12-2011 07:03 PM

Given that you are talking about generics, you could just calculate the length 'compile-time' using a log2() function (I think you'll have to write the function yourself, but that is trivial)

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