new to VHDL needs help
 

Hi

I what to make a vhdl block that i can continually write to from a 8bit
data bus. the only control signals i what to use are notCS and notWrite.
Every time i have written 5 bytes, it has to pass these on as a 40 bit bus.

Is this the right way of doing this.
some times there is a bit missing in the 40bit bus

like this
write
aa 55 33 22 ff

40bitbus
aa 54 33 22 ff

not always byte 2.

can someone help ?

thomas

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mapbus is

generic (
bus_8bit : natural := 8;
bits : natural := 8;
bytes : natural := 105

);

port (
-- dbg : out std_logic;
Clk250KHz : in std_logic;
Bus40bitout : out std_logic_vector(39 downto 0);
notReset : in std_logic; -- reset pin
notCS : in std_logic; -- chip select
notWrite : in std_logic; -- notWrite pin
Bus8BitIn : in std_logic_vector(BUS_8BIT -1 downto 0)
); -- input bus
end mapbus;

architecture rtl of mapbus is
-- ram vector type
type vector_array is array ( 0 to bytes -1) of std_logic_vector (bits
-1 downto 0);
signal memory : vector_array; -- ram definition
signal write_addr : natural range 0 to 105;
signal read_addr : natural range 0 to 105;
signal count : natural range 0 to 4;

type vector5bytes is array (0 to 4) of std_logic_vector(bits-1 downto 0);
signal temp5bytes : vector5bytes;

begin -- rtl

--dbg <= count;

-- handle write to memory
process (notCS, notWrite)
begin -- process
if (notWrite = '0') then
if(notCS'event and notCS = '0') then
memory(conv_integer(write_addr)) <= Bus8BitIn;
end if;
end if;
end process;

-- increase write_addr counter
process (notReset, notWrite)
begin -- process
if (notReset = '0') then
write_addr <= 0;
elsif (notWrite'event and notWrite = '1') then
write_addr <= write_addr + 1;
if (write_addr = 105) then
write_addr <= 0;
end if;
end if;
end process;

-- count up 5 bytes and latch 1 byte every read
process (notReset, Clk250KHz)
begin -- process
if (notReset = '0') then
count <= 0;
read_addr <= 0;
elsif (Clk250KHz'event and Clk250KHz = '0') then
count <= count + 1;
if (count = 4) then
count <= 0;
end if;

read_addr <= read_addr + 1;
if (read_addr = 105) then
read_addr <= 0;
end if;

case count is
when 0 => temp5words(0) <= memory(conv_integer(read_addr));
when 1 => temp5words(1) <= memory(conv_integer(read_addr));
when 2 => temp5words(2) <= memory(conv_integer(read_addr));
when 3 => temp5words(3) <= memory(conv_integer(read_addr));

when 4 => temp5words(4) <= memory(conv_integer(read_addr));
end case;

end if;
end process;


-- latch 40bits when count = 4
process (Clk250KHz,count)
begin -- process
if (Clk250KHz'event and Clk250KHz = '0') then
if (count = 4) then
Bus40BitOut <= temp5words(0) & temp5words(1) & temp5words(2)
& temp5words(3) & temp5words(4);
end if;
end if;
end process;

end rtl;

Re: new to VHDL needs help
 

You are using three clocks in this block working without interlocks,
its not surprising that you are getting errors. probably there is
something wrong in what is required or your understanding of it.

Re: new to VHDL needs help
 

Neo wrote:
> You are using three clocks in this block working without interlocks,
> its not surprising that you are getting errors. probably there is
> something wrong in what is required or your understanding of it.
>

It works now, my testbench was off :)

but what is interlocks ?.

can you post at link to a description ?

--
thomas