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Divyang M 05-15-2005 05:38 AM

State machine transition on internal signals -- is it legal?
 
Hi,

I am coding a state machine and have the transition from one state to
the next (or back to the same state) conditional on an internal signal.
The internal signal is essentially a counter. Is this OK to do and is
it synthesizable? Any forseen problems with it?

Here is a snippet of the state machine (one process type).
process(clk, rst) -- sensitivity list
"newline" is an INPUT port
"mydelay", "vert", and "horiz" are SIGNALs

when WAIT_16 =>
if newline = '1' then
mydelay <= mydelay + 1;
end if;

if mydelay < 16 then
next_state <= WAIT_16;
else
next_state <= DO_PROCESSING;
end if;

when DO_PROCESSING =>
if horiz < 640 then
horiz <= horiz + 1;
next_state <= DO_PROCESSING;
else
next_state <= WAIT_FOR_NEWLINE;
end if;

when WAIT_FOR_NEWLINE =>
if newline = '1' then
if vert < 240 then
vert <= vert + 1;
else
vert <= 0;
end if;
horiz <= 0;
next_state <= DO_PROCESSING;
else
next_state <= WAIT_FOR_NEWLINE;
end if;

end case;

Thanks,
Divyang M


Jerzy Gbur 05-15-2005 09:36 AM

Re: State machine transition on internal signals -- is it legal?
 
Divyang M wrote:
> Hi,
>
> I am coding a state machine and have the transition from one state to
> the next (or back to the same state) conditional on an internal signal.
> The internal signal is essentially a counter. Is this OK to do and is
> it synthesizable? Any forseen problems with it?
>
> Here is a snippet of the state machine (one process type).
> process(clk, rst) -- sensitivity list
> "newline" is an INPUT port
> "mydelay", "vert", and "horiz" are SIGNALs
>
> when WAIT_16 =>
> if newline = '1' then
> mydelay <= mydelay + 1;
> end if;
>
> if mydelay < 16 then
> next_state <= WAIT_16;
> else
> next_state <= DO_PROCESSING;
> end if;
>
> when DO_PROCESSING =>
> if horiz < 640 then
> horiz <= horiz + 1;
> next_state <= DO_PROCESSING;
> else
> next_state <= WAIT_FOR_NEWLINE;
> end if;
>
> when WAIT_FOR_NEWLINE =>
> if newline = '1' then
> if vert < 240 then
> vert <= vert + 1;
> else
> vert <= 0;
> end if;
> horiz <= 0;
> next_state <= DO_PROCESSING;
> else
> next_state <= WAIT_FOR_NEWLINE;
> end if;
>
> end case;


On the first glance it should work.

regards

Jerzy Gbur


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