Can real number be synthesized
 

Hi,

The textbook says the real number in the vhdl code can not be
synthesized. Is it correct? The example in the textbook is:

signal x: REAL := 2.5;
Begin
x <= x/3.0;

It says that the Lieteral 'of type REAL' is not supported for
synthesis. If this is true, how to implement real number operations in
vhdl?

Kuan

Re: Can real number be synthesized
 

Hi Kuan,

At present tools cannot synthesize real numbers . Normally real
numbers are represented in fixed point format for synthesis.
Fixed point numbers are again represented as std_logic_vector with a
decimal point in between. User is reponsible to know where is the
decimal point and arithmetic operations done on it

There are fixed point packages availabe which does this work for you
but I have not used it yet ..

http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html

Kuan I would suggest you to learn the basics of digital arithmetic
before you implement in hardware.

Re: Can real number be synthesized
 

In article <1114160911.867234.143460@o13g2000cwo.googlegroups .com>,
Mohammed A khader <am.imak@gmail.com> wrote:
>Hi Kuan,
>
> At present tools cannot synthesize real numbers . Normally real
>numbers are represented in fixed point format for synthesis.
> Fixed point numbers are again represented as std_logic_vector with a
>decimal point in between. User is reponsible to know where is the
>decimal point and arithmetic operations done on it
>
> There are fixed point packages availabe which does this work for you
>but I have not used it yet ..
>
> http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html
>

The fixed_pkg listed on that web page will work fine in simulation and
with many synthesis tools, but be warned: it will not work with Xilinx's
XST synth tools due to a bug in XST (it's not able to handle negative
indices in ranges).

Phil