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 bxbxb3 03-18-2005 03:31 AM

problem with loop statement

Hi,
Could anyone help me out with this probelm? When ever I try to simulate
the code shown below, my ModelSIM hangs up!

My code is a simple one.

process(clk)
begin
if(clk'event and clk='1') then
if reset='1' then
reg<="000000000000000000000000000000000"; --reg is 33 bits wide(32
downto 0)
generator<="100000100110000010001110110110111"; --total 33 bits
counter<=0;
else
while(not(counter=63)) loop
reg<=reg(31 downto 0) & '0';
if(reg(31)='1') then
reg<=reg xor generator;
end if;
end loop;
end if;
end if;
end process;

 bxbxb3 03-18-2005 03:45 AM

Re: problem with loop statement

Sorry, I forgot to mention
counter<=counter+1; after "end if" statement in the while loop.
Thanks.

 Jezwold 03-18-2005 07:12 AM

Re: problem with loop statement

The problem is in the fact that you are trying to shift 'reg' left 63
times on the rising edge of the clk signal I would have thought.

 Jezwold 03-18-2005 07:31 AM

Re: problem with loop statement

Well o.k 64 times.

 ALuPin 03-18-2005 08:28 AM

Re: problem with loop statement

You are trying to increment the SIGNAL counter in a loop within
one clock cycle! You need one VARIABLE.

process(clk)
variable counter : integer range 0 to 63
begin
if rising_edge(clk) then
if reset='1' then
reg <="000000000000000000000000000000000";
generator <="100000100110000010001110110110111";
else
counter := 0;
while(not(counter=63)) loop
reg <= reg(31 downto 0) & '0';
if reg(31)='1' then
reg <= (reg xor generator);
end if;
counter := counter+1;
end loop;
end if;
end if;
end process;

You should always remeber that the change of a signal in one clock cycle
only takes effect one clock cycle later!

What are you trying to implement ?

Rgds
André

 Jezwold 03-18-2005 08:34 AM

Re: problem with loop statement

The fact is he is trying to do lots of stuff within one clock cycle.

 bxbxb3 03-18-2005 10:24 AM

Re: problem with loop statement

Got it! I must not do so many shifts in a signal clock tick. Actually I
thought the counter in the while loop would increment every clock cycle.

 bxbxb3 03-18-2005 10:57 AM

Re: problem with loop statement

Actually I was trying to develop a code for 32-bit serial CRC generation. I
tried the recommended one and was just checking other methods to do the
same. One of the codes looks like this:

process(clk)
begin
if(clk'event and clk='1') then
if(init='1') then
i<=63;
j<=31;
reg<=data_in & "00000000000000000000000000000000";
generator_poly<="100000100110000010001110110110111 ";
elsif(init='0') then
i<=i-1;
j<=j-1;
if(reg(i)='1' and i>31) then
reg(i downto j)<=reg(i downto j) xor generator_poly;
elsif(i=31) then
i<=63;
j<=31;
crc_out<=reg(31 downto 0);
end if;
end if;
end if;
end process;

The above code does not synthesis because of (i downto j) clause.

 Peter Hermansson 03-18-2005 01:24 PM

Re: problem with loop statement

> Hi,
> Could anyone help me out with this probelm? When ever I try to simulate
> the code shown below, my ModelSIM hangs up!
>
> My code is a simple one.
>
> process(clk)
> begin
> if(clk'event and clk='1') then
> if reset='1' then
> reg<="000000000000000000000000000000000"; --reg is 33 bits wide(32
> downto 0)
> generator<="100000100110000010001110110110111"; --total 33 bits
> counter<=0;
> else
> while(not(counter=63)) loop
> reg<=reg(31 downto 0) & '0';
> if(reg(31)='1') then
> reg<=reg xor generator;
> end if;
> end loop;
> end if;
> end if;
> end process;

Hi,

Lets say your counter does not equal 63. Then you have (I believe) an
endless loop executing reg <= reg(31 downto 0) & '0';
Why not try a FOR LOOP instead?

Another suggestion: reg could be cleared with reg <= (others => '0');

/Peter

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