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-   -   XST: How to select the architecture for synthesis? (http://www.velocityreviews.com/forums/t23401-xst-how-to-select-the-architecture-for-synthesis.html)

Mathias Schmalisch 02-23-2005 12:02 PM

XST: How to select the architecture for synthesis?
 
Hi,

I have an VHDL toplevel entity with multiple architectures. If I try
to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
then only the last architecture will be synthesized.

Therefore my question: Is it possible to select the architecture that
will be synthesized and how this work?

Best Regards
Mathias

Tuukka Toivonen 02-23-2005 12:49 PM

Re: XST: How to select the architecture for synthesis?
 
On 2005-02-23, Mathias Schmalisch <schmalisch@yahoo.de> wrote:
> I have an VHDL toplevel entity with multiple architectures. If I try
> to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
> then only the last architecture will be synthesized.
>
> Therefore my question: Is it possible to select the architecture that
> will be synthesized and how this work?


In principle you can do that in VHDL using the
configuration specification like

for all : xxx use entity yyy(rtl)

...but my experience is that very few of synthesis programs support it.
At least Synopsys Design Compiler doesn't. I don't know a better
solution except that just to comment out other architectures and leave
just one. If anyone knows a better way, let me know.

Ansgar Bambynek 02-23-2005 02:38 PM

Re: How to select the architecture for synthesis?
 
Hi,

any particular reason why you do have several architectures within your
entity?

Usually as you have already mentioned the last architecture gets
synthesized.
You might check the XST manuals or the Xilinx homepage if pragmas might
help.

According to the constraints guide for ise6.3i p. 821 xst can handle
translate_on and translate_off.
The constraints guide is downloadable as zipped pdf from the XILINX homepage

HTH

Ansgar

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Attention please, reply address is invalid, please remove "_xxx_" ro reply
"Mathias Schmalisch" <schmalisch@yahoo.de> schrieb im Newsbeitrag
news:962628c0.0502230402.6158e525@posting.google.c om...
> Hi,
>
> I have an VHDL toplevel entity with multiple architectures. If I try
> to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
> then only the last architecture will be synthesized.
>
> Therefore my question: Is it possible to select the architecture that
> will be synthesized and how this work?
>
> Best Regards
> Mathias




Walter Dvorak 02-23-2005 02:47 PM

Re: XST: How to select the architecture for synthesis?
 
In comp.arch.fpga Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid> wrote:
> I don't know a better solution except that just to comment out other architectures
> and leave just one. If anyone knows a better way, let me know.


A "pre-compiler" before the synthesis tool is no option? Some
very nice conditional synthesis is also possible with text tools
like:

gnu-make, awk/sed or m4. Just as a hint...

WD
--

Hal Murray 02-26-2005 10:46 PM

Re: XST: How to select the architecture for synthesis?
 
> A "pre-compiler" before the synthesis tool is no option? Some
>very nice conditional synthesis is also possible with text tools
>like:
>
> gnu-make, awk/sed or m4. Just as a hint...


The standard c pre processor that handles #if, #ifdef and #define
works on any input file.

try man cpp

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