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=?ISO-8859-1?Q?Andr=E9s?= 02-22-2005 12:34 PM

Pin declarations in EC/ECP FPGAs
 
Hello newsgroup people,

I am facing some problems when having the following pin declarations in
my VHDL top level file.

(ispLEVER version 4.2)
(device LFEC20E-5F672CES)

ATTRIBUTE PINL : STRING;
ATTRIBUTE PINL OF Rst : SIGNAL IS "V25";
ATTRIBUTE PINL OF Clk_board : SIGNAL IS "V20";
ATTRIBUTE PINL OF Sdram_clk_out_p : SIGNAL IS "A15";
ATTRIBUTE PINL OF Sdram_clk_out_n : SIGNAL IS "B15";
ATTRIBUTE PINL OF Sdram_cke : SIGNAL IS "E17, B17";
ATTRIBUTE PINL OF Sdram_csn : SIGNAL IS "A24, A23";
ATTRIBUTE PINL OF Sdram_wen : SIGNAL IS "B22";
ATTRIBUTE PINL OF Sdram_casn : SIGNAL IS "A22";
ATTRIBUTE PINL OF Sdram_rasn : SIGNAL IS "A21";
ATTRIBUTE PINL OF Sdram_addr : SIGNAL IS "D19, A18, E20, E18, B18,
F18, D18, F19, C18, G18, A19, G19, B19";
ATTRIBUTE PINL OF Sdram_ba : SIGNAL IS "B20, B21";
ATTRIBUTE PINL OF Sdram_dqm : SIGNAL IS "E16, F15";
ATTRIBUTE PINL OF Sdram_dqs : SIGNAL IS "A20, G15";
ATTRIBUTE PINL OF Sdram_dq : SIGNAL IS "C17, D17, C16, D16, F17,
G17, F16, G16, C15, B16, C14, E14, D15, E15, F14, G14";

When compiling I get the following warning message:
>Warning, attribute PINL given large bit vector width, potentially
>unacceptable by place and route tools. Consider a string attribute
>instead


Unfortunately I cannot find any answer in the HELP menu.

Has someone of you faced a similar problem ?

Thank you in advance.

Rgds

Mike Treseler 02-22-2005 03:04 PM

Re: Pin declarations in EC/ECP FPGAs
 
Andrés wrote:

> ATTRIBUTE PINL OF Sdram_dq : SIGNAL IS "C17, D17, C16, D16, F17,
> G17, F16, G16, C15, B16, C14, E14, D15, E15, F14, G14";
>
> When compiling I get the following warning message:
> >Warning, attribute PINL given large bit vector width, potentially
> >unacceptable by place and route tools. Consider a string attribute
> >instead


Consider commenting out all of the attributes from your vhdl sources.
Once you have an error-free synthesis, find the text file
with the pin assignments, and edit that.

-- Mike Treseler

cristian 02-22-2005 07:52 PM

Re: Pin declarations in EC/ECP FPGAs
 
Andres,

I think the problem is the 'PINL' string you are using.

Here is a pin assignment that works for me:

--The syntax of attribute LOC
--attribute LOC : string;
--attribute LOC of [SigName] : signal is "P[pin#]";

attribute LOC : string;
attribute LOC of in5 : signal is "W24";
attribute LOC of in8 : signal is "W22";
attribute LOC of in10 : signal is "A15";
attribute LOC of o : signal is "D19, A18, E18";

You can get information on this and other attributes in:
File->Open Example->CPLD-> Constraints or
File->Open Example->Lattice EC->Preferences_attributes

Regards,

cristian


=?ISO-8859-1?Q?Andr=E9s?= 02-23-2005 10:15 AM

Re: Pin declarations in EC/ECP FPGAs
 
cristian wrote:
> Andres,
>
> I think the problem is the 'PINL' string you are using.
>
> Here is a pin assignment that works for me:
>
> --The syntax of attribute LOC
> --attribute LOC : string;
> --attribute LOC of [SigName] : signal is "P[pin#]";
>
> attribute LOC : string;
> attribute LOC of in5 : signal is "W24";
> attribute LOC of in8 : signal is "W22";
> attribute LOC of in10 : signal is "A15";
> attribute LOC of o : signal is "D19, A18, E18";
>
> You can get information on this and other attributes in:
> File->Open Example->CPLD-> Constraints or
> File->Open Example->Lattice EC->Preferences_attributes
>
> Regards,
>
> cristian
>

Did you try that with the EC/ECP family?
When using LOC instead of PINL I still get the warning.

Rgds
Andrés

cristian 02-24-2005 05:38 AM

Re: Pin declarations in EC/ECP FPGAs
 
Andres,

I am targeting the same part that you use and using 4.2 as well (have
you installed SP1 yet? ). I've increased the bus width to 32 and other
one to 16 and I do not have any problem assingning the pins with the
above attribute.
One point I discovered is that you have to declare the pin # all in the
same line. Do not use enter (< > ) to make the code more readable.
If still having problems, follow what Mike mentioned, until finding the
line generating the warning and work on that particular pin assignment.
After trying that and still with warnings, you should call your local
FAE to find out the source of the warnings.

regards,

cristian


Vinzent 'Gadget' Hoefler 02-24-2005 07:23 AM

Re: Pin declarations in EC/ECP FPGAs
 
cristian wrote:

> One point I discovered is that you have to declare the pin # all in
> the same line. Do not use enter (< > ) to make the code more readable.


It's a string. Try the "&"-function instead.


Vinzent.

--
worst case: The wrong assumption there actually is one.

=?ISO-8859-1?Q?Andr=E9s?= 02-24-2005 01:14 PM

Re: Pin declarations in EC/ECP FPGAs
 
cristian wrote:
> Andres,
>
> I am targeting the same part that you use and using 4.2 as well (have
> you installed SP1 yet? ). I've increased the bus width to 32 and other
> one to 16 and I do not have any problem assingning the pins with the
> above attribute.
> One point I discovered is that you have to declare the pin # all in the
> same line. Do not use enter (< > ) to make the code more readable.
> If still having problems, follow what Mike mentioned, until finding the
> line generating the warning and work on that particular pin assignment.
> After trying that and still with warnings, you should call your local
> FAE to find out the source of the warnings.
>
> regards,
>
> cristian
>

Hi Cristian,

I am trying to put into operation the Lattice EC Advanced Evaluation
Board (Revision C).

How do I know whether SP1 is installed ?

Under Help I find the following:

ispLEVER Service Pack SP4.2.01.50.50.04
ispLEVER Production Build 4.2.00.39.43.04

Concerning the pin declarations I used the Pre-Map Preference Editor.
By the way some additional questions:

How do you handle the RESET phase of your FPGA ? Do you use some
WATCHDOG strategy that is an external WATCHDOG generates the RESET
signal for the FPGA whereas the FPGA feeds the WATCHDOG with a periodic
signal ?

Are there dedicated Pins for Asynchronous Reset inputs?


Rgds
Andrés

cristian 02-25-2005 05:49 AM

Re: Pin declarations in EC/ECP FPGAs
 
Andres,

It looks like you have SP1 installed. For future updates you can use
the ispUPDATE utility available from: Start->Programs->Lattice
Semiconductor-> ispUPDATE

Regarding the RESET and the WATCHDOG, well that is up to you. Of course
you can implement that configuration when using the EC/ECP. I see no
issue at all.
In the EC/ECP family any I/O pin can be the Global Asynchronous
Reset/Set (GSRN, active low) . Take a look at TN1008 page 14-13.

rgds,

cristian


=?ISO-8859-1?Q?Andr=E9s?= 02-25-2005 01:10 PM

Re: Pin declarations in EC/ECP FPGAs
 
cristian wrote:
> Andres,
>
> It looks like you have SP1 installed. For future updates you can use
> the ispUPDATE utility available from: Start->Programs->Lattice
> Semiconductor-> ispUPDATE
>
> Regarding the RESET and the WATCHDOG, well that is up to you. Of course
> you can implement that configuration when using the EC/ECP. I see no
> issue at all.
> In the EC/ECP family any I/O pin can be the Global Asynchronous
> Reset/Set (GSRN, active low) . Take a look at TN1008 page 14-13.
>
> rgds,
>
> cristian
>

Hi Cristian,

I had a look at the paper and it is said that "it can be activated
either by an external dedicated pin ..." So not any I/O pin can be the
Global Asynchronous Reset, Set ?

It is said further that "It can be activated either ... or from internal
logic after configuration". But it is not said how to access this
internal signal ...
Do you have any idea how to access it? Some component instantiation of
some special module ?

rgds,

Andrés



cristian 02-26-2005 12:53 AM

Re: Pin declarations in EC/ECP FPGAs
 
Andres,

It looks confused to me as well, but again any I/O pin can be used as
GSRN.

On the other question, if you see the example on page 14.14 it
instantiates the GSR component. That basically is just an ouptut that
is connected to the global reset signal. That is the way to activate
the reset after configuration.

rgds,

cristian



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