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Cor van Loos 12-08-2004 07:15 PM

Instantiation of lots of the some component
 
For a very simple design I need to instantiate a lot of components. Only
two of the I/O signals of these components differ. Is there a smart way
to do this in VHDL or do I have to make a 100 copies to instatiate 100
components?


Cor

Mike Treseler 12-08-2004 08:19 PM

Re: Instantiation of lots of the some component
 
Cor van Loos wrote:
> For a very simple design I need to instantiate a lot of components. Only
> two of the I/O signals of these components differ. Is there a smart way
> to do this in VHDL or do I have to make a 100 copies to instatiate 100
> components?


Instances will work, but consider using a FOR loop.

-- Mike Treseler

cas7406@yahoo.com 12-09-2004 05:53 AM

Re: Instantiation of lots of the some component
 

Mike Treseler wrote:
> Cor van Loos wrote:
> > For a very simple design I need to instantiate a lot of components.

Only
> > two of the I/O signals of these components differ. Is there a smart

way
> > to do this in VHDL or do I have to make a 100 copies to instatiate

100
> > components?

>
> Instances will work, but consider using a FOR loop.
>
> -- Mike Treseler


Cor,
I'd use GENERATE:
-- instantiate basic_9x9 four times
generate_4_9x9:
FOR i IN 0 to 3 GENERATE
m0: basic_9x9 port map(data(i*2), data(i*2+1), rst_0, clk,
result_mult(i));
END GENERATE;

cristian



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